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48th MICRO 2015: Waikiki, HI, USA
- Milos Prvulovic:
Proceedings of the 48th International Symposium on Microarchitecture, MICRO 2015, Waikiki, HI, USA, December 5-9, 2015. ACM 2015, ISBN 978-1-4503-4034-2
Best paper candidates
- Binh Pham, Ján Veselý, Gabriel H. Loh, Abhishek Bhattacharjee:
Large pages and lightweight memory management in virtualized environments: can you have it both ways? 1-12 - Guowei Zhang, Webb Horn, Daniel Sánchez:
Exploiting commutativity to reduce the cost of updates to shared data in cache-coherent systems. 13-25 - Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi:
CCICheck: using µhb graphs to verify the coherence-consistency interface. 26-37
Cache
- Angelos Arelakis, Fredrik Dahlgren, Per Stenström:
HyComp: a hybrid cache compression method for selection of data-type-specific compression methods. 38-49 - Joshua San Miguel, Jorge Albericio, Andreas Moshovos, Natalie D. Enright Jerger
:
Doppelgänger: a cache for approximate computing. 50-61 - Lavanya Subramanian, Vivek Seshadri, Arnab Ghosh, Samira Manabi Khan, Onur Mutlu:
The application slowdown model: quantifying and controlling the impact of inter-application interference at shared caches and main memory. 62-75 - Tri Minh Nguyen, David Wentzlaff:
MORC: a manycore-oriented compressed cache. 76-88
Security
- Ali Shafiee, Akhila Gundu, Manjunath Shevgoor, Rajeev Balasubramonian, Mohit Tiwari
Avoiding information leakage in the memory controller with fixed service policies. 89-101 - Xian Zhang, Guangyu Sun, Chao Zhang, Weiqi Zhang, Yun Liang, Tao Wang, Yiran Chen, Jia Di:
Fork path: improving efficiency of ORAM by removing redundant memory accesses. 102-114 - William Arthur, Sahil Madeka, Reetuparna Das
Locking down insecure indirection with hardware-based control-data isolation. 115-127 - Anys Bacha, Radu Teodorescu:
Authenticache: harnessing cache ECC for system authentication. 128-140
Prefetching
- Manjunath Shevgoor, Sahil Koladiya, Rajeev Balasubramonian, Chris Wilkerson, Seth H. Pugsley, Zeshan Chishti:
Efficiently prefetching complex address patterns. 141-152 - Islam Atta, Xin Tong, Vijayalakshmi Srinivasan, Ioana Baldini, Andreas Moshovos:
Self-contained, accurate precomputation prefetching. 153-165 - Cansu Kaynak, Boris Grot
Confluence: unified instruction supply for scale-out servers. 166-177 - Xiangyao Yu, Christopher J. Hughes
IMP: indirect memory prefetcher. 178-190
Concurrency
- Tae Jun Ham, Juan L. Aragón
DeSC: decoupled supply-compute communication management for heterogeneous architectures. 191-203 - Farzad Khorasani, Rajiv Gupta
Efficient warp execution in presence of divergence with collaborative context collection. 204-215 - Dani Voitsechov, Yoav Etsion:
Control flow coalescing on a hybrid dataflow/von Neumann GPGPU. 216-227 - Mark C. Jeffrey
A scalable architecture for ordered parallelism. 228-241
DRAM
- Yanwei Song, Engin Ipek:
More is less: improving the energy efficiency of data movement via opportunistic use of sparse codes. 242-254 - Shih-Lien Lu, Ying-Chen Lin, Chia-Lin Yang
Improving DRAM latency with dynamic asymmetric subarray. 255-266 - Vivek Seshadri, Thomas Mullins, Amirali Boroumand, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry:
Gather-scatter DRAM: in-DRAM address translation to improve the spatial locality of non-unit strided accesses. 267-280
Voltage
- Rajib Nath, Dean M. Tullsen
The CRISP performance model for dynamic voltage and frequency scaling in a GPGPU. 281-293 - Jingwen Leng, Alper Buyuktosunoglu, Ramon Bertran
Safe limits on voltage reduction efficiency in GPUs: a direct measurement approach. 294-307 - Yazhou Zu, Charles R. Lefurgy, Jingwen Leng, Matthew Halpern, Michael S. Floyd, Vijay Janapa Reddi:
Adaptive guardband scheduling to improve system-level efficiency of the POWER7+. 308-321
Micro-architecture
- Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke:
DynaMOS: dynamic schedule migration for heterogeneous cores. 322-333 - Andreas Sembrant, Trevor E. Carlson
Long term parking (LTP): criticality-aware resource allocation in OOO processors. 334-346 - André Seznec, Joshua San Miguel, Jorge Albericio:
The inner most loop iteration counter: a new dimension in branch history. 347-357 - Milad Hashemi, Yale N. Patt:
Filtered runahead execution with a runahead buffer. 358-369 - Daniel S. McFarlin, Craig B. Zilles:
Bungee jumps: accelerating indirect branches through HW/SW co-design. 370-382
GPU
- Jiwei Liu, Jun Yang, Rami G. Melhem:
SAWS: synchronization aware GPGPU warp scheduling for multiple independent warp schedulers. 383-394 - Xiaolong Xie, Yun Liang, Xiuhong Li, Yudong Wu, Guangyu Sun, Tao Wang, Dongrui Fan
Enabling coordinated register allocation and thread-level parallelism optimization for GPUs. 395-406 - Guoyang Chen, Xipeng Shen
Free launch: optimizing GPU dynamic kernel launches through thread reuse. 407-419 - Hyeran Jeon, Gokul Subramanian Ravi
GPU register file virtualization. 420-432 - John Kloosterman
WarpPool: sharing requests with inter-warp coalescing for throughput processors. 433-444
Accelerator
- Enrique de Lucas
Ultra-low power render-based collision detection for CPU/GPU systems. 445-456 - Tao Chen, Alexander Rucker, G. Edward Suh
Execution time prediction for energy-efficient hardware accelerators. 457-469 - Lena E. Olson
Border control: sandboxing accelerators. 470-481 - Amir Yazdanbakhsh
Neural acceleration for GPU throughput processors. 482-493 - Zidong Du, Daniel D. Ben-Dayan Rubin
Neuromorphic accelerators: a comparison between neuroscience and machine-learning approaches. 494-507
Mobile & emerging systems
- Daniel Lo, Taejoon Song, G. Edward Suh
Prediction-guided performance-energy trade-off for interactive applications. 508-520 - Gwangmu Lee, Hyunjoon Park, Seonyeong Heo
Architecture-aware automatic computation offload for native applications. 521-532 - Yuanwei Fang, Tung Thanh Hoang, Michela Becchi, Andrew A. Chien:
Fast support for unstructured data processing: the unified automata processor. 533-545 - Ajaykumar Kannan, Natalie D. Enright Jerger
Enabling interposer-based disintegration of multi-core processors. 546-558 - Jaehyung Ahn, Dongup Kwon, Youngsok Kim
DCS: a fast and scalable device-centric server architecture. 559-571
Datacenter
- Panagiota Nikolaou, Yiannakis Sazeides, Lorena Ndreu, Marios Kleanthous:
Modeling the implications of DRAM failures and protection techniques on datacenter TCO. 572-584 - Balajee Vamanan
TimeTrader: exploiting latency tail to save datacenter energy for online search. 585-597 - Harshad Kasture, Davide B. Bartolini
Rubik: fast analytical power management for latency-critical systems. 598-610
Memory systems
- Seong-Lyong Gong, Minsoo Rhu, Jungrae Kim, Jinsuk Chung, Mattan Erez
CLEAN-ECC: high reliability ECC for adaptive granularity memory system. 611-622 - Daehoon Kim, Hwanju Kim, Nam Sung Kim, Jaehyuk Huh:
vCache: architectural support for transparent and isolated virtual LLCs in virtualized environments. 623-634 - Kathryn E. Gray, Gabriel Kerneis, Dominic P. Mulligan
An integrated concurrency and core-ISA architectural envelope definition, and test oracle, for IBM POWER multiprocessors. 635-646
Coherence, consistency, persistency
- Matthew D. Sinclair, Johnathan Alsop, Sarita V. Adve:
Efficient GPU synchronization without scopes: saying no to complex consistency models. 647-659 - Arpit Joshi, Vijay Nagarajan, Marcelo Cintra, Stratis Viglas:
Efficient persist barriers for multicores. 660-671 - Jinglei Ren, Jishen Zhao, Samira Manabi Khan, Jongmoo Choi, Yongwei Wu, Onur Mutlu:
ThyNVM: enabling software-transparent crash consistency in persistent memory systems. 672-685 - Yaosheng Fu, Tri Minh Nguyen, David Wentzlaff:
Coherence domain restriction on large scale systems. 686-698 - Abhayendra Singh, Shaizeen Aga, Satish Narayanasamy
Efficiently enforcing strong memory ordering in GPUs. 699-712
Modeling & characterization
- Kaige Yan, Xingyao Zhang
Characterizing, modeling, and improving the QoE of mobile devices with low battery level. 713-724 - Newsha Ardalani, Clint Lestourgeon, Karthikeyan Sankaralingam, Xiaojin Zhu:
Cross-architecture performance prediction (XAPP) using CPU code to predict GPU performance. 725-737 - Steven Raasch, Arijit Biswas, Jon Stephan, Paul Racunas, Joel S. Emer:
A fast and accurate analytical technique to compute the AVF of sequential bits in a processor. 738-749 - Qi Guo, Tze Meng Low, Nikolaos Alachiotis, Berkin Akin, Larry T. Pileggi, James C. Hoe, Franz Franchetti:
Enabling portable energy efficiency with memory accelerated library. 750-761 - Yuhao Zhu, Daniel Richins, Matthew Halpern, Vijay Janapa Reddi:
Microarchitectural implications of event-driven server-side web applications. 762-774
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