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6th NOCS 2012: Copenhagen, Denmark
- 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Copenhagen, Denmark, 9-11 May, 2012. IEEE Computer Society 2012, ISBN 978-0-7695-4677-3
Session 1: Routing and Arbitration
- Chris Fallin, Greg Nazario, Xiangyao Yu, Kevin Kai-Wei Chang, Rachata Ausavarungnirun, Onur Mutlu:
MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect. 1-10 - Ahmed Abousamra
, Rami G. Melhem, Alex K. Jones
Déjà Vu Switching for Multiplane NoCs. 11-18 - Masoumeh Ebrahimi, Masoud Daneshtalab, Fahimeh Farahnakian, Juha Plosila
HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks. 19-26 - Dan Zhao, Ruizhe Wu:
Overlaid Mesh Topology Design and Deadlock Free Routing in Wireless Network-on-Chip. 27-34
Session 2: Power Modeling and Power Management in NoCs
- Paul Bogdan
An Optimal Control Approach to Power Management for Multi-Voltage and Frequency Islands Multiprocessor Platforms under Highly Variable Workloads. 35-42 - Xi Chen, Zheng Xu, Hyungjun Kim, Paul Gratz
In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches. 43-50 - Pierre Schamberger, Zhonghai Lu, Xianyang Jiang, Meikang Qiu:
Modeling and Power Evaluation of On-Chip Router Components in Spintronics. 51-58
Session 3: Novel NoC Design & Support for CMP/MPSoCs
- Mario Lodde, José Flich
Heterogeneous NoC Design for Efficient Broadcast-based Coherence Protocol Support. 59-66 - Stavros Volos, Ciprian Seiculescu, Boris Grot
CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers. 67-74 - Gul N. Khan
Synthesis of NoC Interconnects for Custom MPSoC Architectures. 75-82 - Snaider Carrillo
Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations. 83-90
Session 4: Simulation and Analysis
- Javier Navaridas
Reservation-based Network-on-Chip Timing Models for Large-scale Architectural Simulation. 91-98 - Pablo Abad Fidalgo
TOPAZ: An Open-Source Interconnection Network Simulator for Chip Multiprocessors and Supercomputers. 99-106 - Nikita Nikitin, Javier de San Pedro
Analytical Performance Modeling of Hierarchical Interconnect Fabrics. 107-114
Session 5: Flow Control and Flit Serialization
- Zhonghai Lu, Yi Wang:
Dynamic Flow Regulation for IP Integration on Network-on-Chip. 115-123 - Changlin Chen, Ye Lu, Sorin Dan Cotofana
A Novel Flit Serialization Strategy to Utilize Partially Faulty Links in Networks-on-Chip. 124-131 - Robert Hesse, Jeff Nicholls, Natalie D. Enright Jerger
Fine-Grained Bandwidth Adaptivity in Networks-on-Chip Using Bidirectional Channels. 132-141
Session 6: QoS, Error Control and Verification
- Yao Wang, G. Edward Suh:
Efficient Timing Channel Protection for On-Chip Networks. 142-151 - Martin Schoeberl
A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems. 152-160 - Georgios Tsiligiannis
A Mixed Verification Strategy Tailored for Networks on Chip. 161-168 - Qiaoyan Yu, José Cano
Transient and Permanent Error Control for High-End Multiprocessor Systems-on-Chip. 169-176
Session 7: 3D & Emerging NoCs
- Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Khalid Latif, Pasi Liljeberg, Juha Plosila
Generic Monitoring and Management Infrastructure for 3D NoC-Bus Hybrid Architectures. 177-184 - Luca Ramini, Davide Bertozzi, Luca P. Carloni:
Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints. 185-192 - Hyunjun Jang, Baik Song An, Nikhil Kulkarni, Ki Hwan Yum, Eun Jung Kim:
A Hybrid Buffer Design with STT-MRAM for On-Chip Interconnects. 193-200 - Chen Sun, Chia-Hsin Owen Chen, George Kurian, Lan Wei, Jason E. Miller, Anant Agarwal, Li-Shiuan Peh, Vladimir Stojanovic:
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling. 201-210
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