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ASAP 2003: The Hague, The Netherlands
- 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands. IEEE Computer Society 2003, ISBN 0-7695-1992-X
Keynote
- Ruby B. Lee:
Challenges in the Design of Security-Aware Processors. 2-
Models, Methods and Tools
- Hylke W. van Dijk, Henk J. Sips, Ed F. Deprettere:
Context-Aware Process Networks. 6-16 - Sven Verdoolaege, Maurice Bruynooghe, Gerda Janssens, Francky Catthoor:
Multi-dimentsional Incremetal Loops Fusion for Data Locality. 17-27 - Lakshminarayanan Renganarayanan, Sanjay V. Rajopadhye:
Switched Memory Architectures-Moving Beyond Systolic Arrays. 28-39 - Anne-Claire Guillou, Patrice Quinton, Tanguy Risset:
Hardware Synthesis for Multi-Dimensional Time. 40-50 - Thorsten Dräger, Gerhard P. Fettweis:
Using Group Theory to Specify Application Specific Interconnection Networks for SIMD DSPs. 51-
Design Methodology
- Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke:
Systematic Register Bypass Customization for Application-Specific Processors. 64-74 - Alexandru Turjan, Bart Kienhuis:
Storage Management in Process Networks using the Lexicographically Maximal Preimage. 75-85 - José L. Ayala
, Marisa Luisa López-Vallejo
Energy Aware Register File Implementation through Instruction Predecode. 86-96 - Terry Tao Ye
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics. 97-107 - Armita Peymandoust, Laura Pozzi, Paolo Ienne, Giovanni De Micheli
Automatic Instruction Set Extension and Utilization for Embedded Processors. 108-
Nanocomputing Technology and Systems
- Toshishige Yamada
Nanotechnology in the Development of Future Computing Systems. 120-124 - David B. Janes, Subhasis Ghosh
Circuit Characteristics of Molecular Electronic Components. 125-131 - Seth Copen Goldstein, Mihai Budiu, Mahim Mishra, Girish Venkataramani:
Reconfigurable Computing and Electronic Nanotechnology. 132-
Processors
- James Irwin, Dan Page:
Using Media Processors for Low-Memory AES Implementation. 144-154 - Piia Simonen, Ilkka Saastamoinen, Jari Nurmi
Variable-Length Instruction Compression for Area Minimization. 155-160 - Andreas Wieferink, Tim Kogel, Achim Nohl, Andreas Hoffmann:
Generic Tool-Set for SoC Mulitiprocessor Debugging and Synchronization. 161-171 - Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
Evaluating Memory Architectures for Media Applications on Coarse-Grained Recon.gurable Architectures. 172-182 - Rama Sangireddy, Arun K. Somani:
Application-Specific Computing with Adaptive Register File Architectures. 183-
Numeric Co-Processors
- Zhaohui Liu, Kevin Dickson, John V. McCanny:
A floating-point CORDIC based SVD processor. 194-203 - Michael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George Walters III, John Glossner:
Combined Multiplication and Sum-of-Squares Units. 204-214 - Abhishek Singh, Dhananjay S. Phatak, Tom Goff, Mike Riggs, James F. Plusquellic, Chintan Patel:
Comparison of Branching CORDIC Implementations. 215-225 - Lai-Sze Au, Neil Burgess:
Unified Radix-4 Multiplier for GF(p) and GF(2^n). 226-236 - Zhijie Shi, Xiao Yang, Ruby B. Lee:
Arbitrary Bit Permutations in One or Two Cycles. 237-
Multimedia Architectures
- Mihai Sima, Stamatis Vassiliadis, Sorin Cotofana
Color Space Conversion for MPEG decoding on FPGA-augmented TriMedia Processor. 250-259 - Vikram Chandrasekhar, Frank Livingston, Joseph R. Cavallaro
Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers. 260-270 - P. H. Chan, Jack Y. B. Lee:
An Efficient Disk-Array-Based Server Design for a Multicast Video Streaming System. 271-281 - Jung-Yup Kang, Sandeep Gupta, Saurabh Shah, Jean-Luc Gaudiot:
An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation. 282-292 - Swee Yeow Yap, John V. McCanny:
A VLSI Architecture for Advanced Video Coding Motion Estimation. 293-
Computer Arithmetic
- Jean-Michel Muller
Complex Division with Prescaling of Operands. 304-314 - Mark G. Arnold:
Iterative Methods for Logarithmic Subtraction. 315-525 - Giorgos Dimitrakopoulos
A Family of Parallel-Pre.x Modulo 2n - 1 Adders. 326-336 - Chichyang Chen, Rui-Lin Chen:
Performance-Improved Computation of Very Large Word-Length LNS Addition/Subtraction Using Signed-Digit Arithmetic. 337-347 - Mark A. Erle, Michael J. Schulte:
Decimal Multiplication Via Carry-Save Addition. 348-
Signal Processing Architectures
- Yiqun Zhu, Mohammed Benaissa:
Reconfigurable Viterbi Decoding Using a New ACS Pipelining Technique. 360-368 - Kyung Lan Heo, Sung M. Cho, Jung Hoo Lee, Myung Hoon Sunwoo:
Application-Specific DSP Architecture For Fast Fourier Transform. 369-377 - Ayman M. El-Khashab, Earl E. Swartzlander Jr.:
An Architecture for a Radix-4 Modular Pipeline Fast Fourier Transform. 378-388 - George Kornaros
GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks. 389-399 - Viktor Bunimov, Manfred Schimmler:
Area and Time Efficient Modular Multiplication of Large Integers. 400-
Cryptography
- Jean-Luc Beuchat
Modular Multiplication for FPGA Implementation of the IDEA Block Cipher. 412-422 - Guido Bertoni
Concurrent Fault Detection in a Hardware Implementation of the RC5 Encryption Algorithm. 423-432 - Siddika Berna Örs
Hardware Implementation of an Elliptic Curve Processor over GF(p). 433-443 - Hans Eberle, Nils Gura, Sheueling Chang Shantz:
A Cryptograhpic Processor for Arbitrary Elliptic Curves over. 444-454 - Johann Großschädl, Guy-Armand Kamendje:
Instruction Set Extension for Fast Elliptic Curve Cryptography over Binary Finite Fields GF(2m). 455-
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