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12th FMCAD 2012: Cambridge, UK
- Gianpiero Cabodi, Satnam Singh:
Formal Methods in Computer-Aided Design, FMCAD 2012, Cambridge, UK, October 22-25, 2012. IEEE 2012, ISBN 978-1-4673-4832-4
Tutorials
- Jasmin Fisher:
Formal methods in cell Biology. 1 - Torsten Schaub:
Answer Set Programming. 2 - Eric Feron:
Formal methods for aerospace applications. 3 - Alessandro Cimatti:
Application of SMT solvers to hybrid system verification. 4
Keynote
- Tony Hoare:
Algebra of concurrent design. 5
Concurrent Software Verification
- Arnab Sinha, Sharad Malik
, Aarti Gupta
Efficient predictive analysis for detecting nondeterminism in multi-threaded programs. 6-15 - Vineet Kahlon:
Automatic lock insertion in concurrent programs. 16-23 - Parosh Aziz Abdulla, Mohamed Faouzi Atig, Othmane Rezine, Jari Stenman:
Multi-pushdown systems with budgets. 24-33
SAT and Model Checking Algorithms
- Eugene Goldberg, Panagiotis Manolios:
Quantifier elimination by Dependency Sequents. 34-43 - Krystof Hoder, Zurab Khasidashvili, Konstantin Korovin, Andrei Voronkov:
Preprocessing techniques for first-order clausification. 44-51 - Koen Claessen, Niklas Sörensson:
A liveness checking algorithm that counts. 52-59
Machine Code and Memory Verification
- Warren A. Hunt Jr., Matt Kaufmann:
A formal model of a large memory that supports efficient execution. 60-67 - Rohit Sinha, Cynthia Sturton, Petros Maniatis, Sanjit A. Seshia, David A. Wagner:
Verification with small and short worlds. 68-77 - Magnus O. Myreen, Michael J. C. Gordon, Konrad Slind:
Decompilation into logic - Improved. 78-81
Formal Methods for Synthesis, Test and Debug
- Stefan Frehse, Görschwin Fey, Eli Arbel, Karen Yorav, Rolf Drechsler:
Complete and effective robustness checking by means of interpolation. 82-90 - Rüdiger Ehlers, Robert Könighofer, Georg Hofferek:
Symbolically synthesizing small circuits. 91-100 - Brian Keng, Andreas G. Veneris:
Automated debugging of missing input constraints in a formal verification environment. 101-105
Software and Behavioural Hardware Verification
- Dirk Beyer, Philipp Wendler:
Algorithms for software model checking: Predicate abstraction vs. Impact. 106-113 - Ondrej Sery, Grigory Fedyukovich, Natasha Sharygina
Incremental upgrade checking by means of interpolation-based function summaries. 114-121 - Alessandro Cimatti, Iman Narasamdya, Marco Roveri:
Verification of parametric system designs. 122-130
Formal Verification Techniques for Arithmetic Circuits and GPUs
- Leopold Haller, Alberto Griggio, Martin Brain, Daniel Kroening:
Deciding floating-point logic with systematic abstraction. 131-140 - Alexey Lvov, Luis Alfonso Lastras-Montaño, Viresh Paruthi, Robert Shadowen, Ali El-Zein:
Formal verification of error correcting circuits using computational algebraic geometry. 141-148 - V. M. Achutha KiranKumar, Aarti Gupta, Rajnish Ghughal:
Symbolic Trajectory Evaluation: The primary validation Vehicle for next generation Intel® Processor Graphics FPU. 149-156
Automated Abstraction/Reduction Techniques
- Jiazhao Xu, Mark Williams, Hari Mony, Jason Baumgartner:
Enhanced reachability analysis via automated dynamic netlist-based hint generation. 157-164 - Chao Yan, Mark R. Greenstreet:
Oscillator verification with probability one. 165-172 - Yakir Vizel, Orna Grumberg, Sharon Shoham:
Lazy abstraction and SAT-based reachability in hardware model checking. 173-181 - Jason Baumgartner, Alexander Ivrii, Arie Matsliah, Hari Mony:
IC3-guided abstraction. 182-185
Invited Talk
- Daryl Stewart:
Formal for everyone - Challenges in achievable multicore design and verification. 186
Solver Applications
- Alessandro Cimatti, Sergio Mover, Stefano Tonetta:
A quantifier-free SMT encoding of non-linear hybrid automata. 187-195 - Yan Zhang, Sriram Sankaranarayanan, Fabio Somenzi:
Piecewise linear modeling of nonlinear devices for formal verification of analog circuits. 196-203 - Yang Yang, Lei Bu, Xuandong Li:
Forward and backward: Bounded model checking of linear hybrid automata from two directions. 204-208
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