default search action
The Journal of VLSI Signal Processing, Volume 40
Volume 40, Number 1, May 2005
- Michael J. Schulte, Shuvra S. Bhattacharyya
, Robert Schreiber:
Guest Editorial. 5-6 - Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere:
Solving Out-of-Order Communication in Kahn Process Networks. 7-18 - Holger Blume
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip. 19-34 - Alain Darte, Guillaume Huard:
New Complexity Results on Array Contraction and Related Problems. 35-55 - Roger D. Chamberlain, Mark A. Franklin, Praveen Krishnamurthy, Abhijit Mahajan:
VLSI Photonic Ring Multicomputer Interconnect: Architecture and Signal Processing Performance. 57-72 - Jeffrey T. Draper, Tim Barrett, Jeff Sondeen, Sumit D. Mediratta, Chang Woo Kang, Ihn Kim, Gokhan Daglikoca:
A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System. 73-84 - Ruby B. Lee, A. Murat Fiskiran:
PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing. 85-108 - José-Alejandro Piñeiro, Milos D. Ercegovac, Javier D. Bruguera:
High-Radix Logarithm with Selection by Rounding: Algorithm and Implementation. 109-123 - Neil Burgess:
New Models of Prefix Adder Topologies. 125-141 - Peter Kornerup:
Reviewing 4-to-2 Adders for Multi-Operand Addition. 143-152
Volume 40, Number 2, June 2005
- Fan Xu, Guichang Zhong, Alan N. Willson Jr.:
Analysis and VLSI Realization of a Blind Beamforming Algorithm. 159-174 - Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters. 175-188 - Rafael Gadea Gironés
FPGA Implementation of a Pipelined On-Line Backpropagation. 189-213 - Jarno K. Tanskanen, Reiner Creutzburg
On Design of Parallel Memory Access Schemes for Video Coding. 215-237 - Sangjin Hong, Shu-Shin Chin:
Domain Specific Reconfigurable Processing Core Architecture for Digital Filtering Applications. 239-259 - Albert Mo Kim Cheng
Reducing Encoder Bit-Rate Variation in MPEG Video. 261-271
Volume 40, Number 3, July 2005
- Myung Hoon Sunwoo, Wonyong Sung:
Guest Editorial. 279-280 - Jung L. Lee, Myung Hoon Sunwoo:
Implementation of a Wireless Multimedia DSP Chip for Mobile Applications. 281-287 - Dong-Ik Ko, Shuvra S. Bhattacharyya
Modeling of Block-Based DSP Systems. 289-299 - Wonyong Sung, Youngho Ahn, Eunjoo Hwang:
VLSI Implementation of An Adaptive Equalizer for ATSC Digital TV Receivers. 301-310 - Finbarr O'Regan, Conor Heneghan:
A Low Power Algorithm for Sparse System Identification using Cross-Correlation. 311-333 - Mehboob Alam
An Efficient Architecture for a Lifted 2D Biorthogonal DWT. 335-342 - Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization. 343-353 - Tarek Darwish, Magdy A. Bayoumi:
Coefficient Elimination Algorithm for Low Energy Distributed Arithmetic DCT Architectures. 355-369 - Mohammad M. Mansour, Naresh R. Shanbhag:
A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes. 371-382 - Marc Leeman, David Atienza, Geert Deconinck
Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications. 383-396
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-01-18 00:50 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: