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Hiroshi Kawaguchi 0001
Person information
- affiliation: Kobe University, Graduate School of Science, Technology and Innovation, Japan
- affiliation (PhD 2006): University of Tokyo, Tokyo, Center for Collaborative Research, Japan
Other persons with the same name
- Hiroshi Kawaguchi 0002
— National Institute of Advanced Industrial Science and Technology, Tsukuba, Japan (and 1 more)
- Hiroshi Kawaguchi 0003 — University of Electro-Communications, Tokyo, Japan
- Hiroshi Kawaguchi 0004 — Nippon Medical School, Department of Legal Medicine, Tokyo, Japan
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2020 – today
- 2024
- [j92]Ryotaro Ohara
MicroSync: Sub-Micro Second Accuracy Wireless Time Synchronization Service. IEEE Access 12: 124478-124494 (2024) - [j91]Ryotaro Ohara, Atsushi Fukunaga, Masakazu Taichi, Masaya Kabuto, Riku Hamabe, Masato Ikegawa, Shintaro Izumi, Hiroshi Kawaguchi:
A Case Study for Improving Performances of Deep-Learning Processor with MRAM. IPSJ Trans. Syst. LSI Des. Methodol. 17: 7-15 (2024) - [c137]Yusaku Goto, Shintaro Izumi, Ryotaro Ohara, Teppei Araki, Sho Murase, Hiroshi Kawaguchi:
15-ch Wearable Body Surface Potential Sensor for Wireless Electrocardiogram Monitoring. ICCE 2024: 1-5 - [c136]Shun Sato, Ryotaro Ohara, M. Shahrul Amir Kamarulzaman, Yuto Yasuda, Shintaro Izumi, Hiroshi Kawaguchi:
An Ultrasound-Based Surveillance System for Bathroom Posture and Location Estimation. ICCE 2024: 1-5 - [c135]Ryo Takamatsu, Shintaro Izumi, Hiroshi Kawaguchi:
Wearable Perspiration Characteristic Sensor Using Bi-Directional Driver Circuit. ICCE 2024: 1-6 - [c134]Yasufumi Sakai, Naoki Matsumura, Atsuki Inoue, Hiroshi Kawaguchi, Thang Dang, Atsushi Ishikawa, Árni Björn Höskuldsson, Egill Skúlason:
Active Learning for Graph Neural Networks Training in Catalyst Energy Prediction. IJCNN 2024: 1-8 - [c133]Koki Mori, Ryotaro Ohara, Takayuki Genda, Shun Sato, Shintaro Izumi, Hiroshi Kawaguchi:
Estimating Human Activities in Bathroom Through Sound Event Detection in Embedded Systems. IOTSMS 2024: 120-123 - 2023
- [c132]Kengo Matsumoto, Tomoya Matsuda, Atsuki Inoue, Hiroshi Kawaguchi, Yasufumi Sakai:
A Mixed-Precision Quantization Method without Accuracy Degradation Using Semilayers. ACML 2023: 882-894 - [c131]Ryotaro Ohara, Masaya Kabuto, Masakazu Taichi, Atsushi Fukunaga, Yuto Yasuda, Riku Hamabe, Shintaro Izumi, Hiroshi Kawaguchi
A 1W8R 20T SRAM Codebook for 20% Energy Reduction in Mixed-Precision Deep-Learning Inference Processor System. AICAS 2023: 1-5 - [c130]Tatsuya Sugimoto
Quantitative Evaluation Method of Timed Up and Go Test for Hospitalized Patients Using Inertial Sensors. BSN 2023: 1-4 - [c129]Tomoya Matsuda, Kengo Matsumoto, Atsuki Inoue, Hiroshi Kawaguchi
Semilayer-Wise Partial Quantization Without Accuracy Degradation or Back Propagation. ICANN (9) 2023: 283-295 - [c128]Yasufumi Sakai, Thang Dang, Shigeki Fukuta, Koichi Shirahata, Atsushi Ishikawa
Self-Supervised Learning with Atom Replacement for Catalyst Energy Prediction by Graph Neural Networks. INNS DLIA@IJCNN 2023: 458-467 - 2022
- [c127]Masayasu Harada, Shintaro Izumi, Ryosuke Kozeni, Yukiko Yoshikawa, Toru Ishii, Hiroshi Kawaguchi
20-µs Accuracy Time-Synchronization Method using Bluetooth Low Energy for Internet-of-Things Sensors. CCNC 2022: 181-186 - [c126]Kazuki Okado, Kengo Matsumoto, Atsuki Inoue, Hiroshi Kawaguchi
Channel-wise quantization without accuracy degradation using Δloss analysis. ICMLT 2022: 56-61 - [c125]Yasufumi Sakai, Akinori Iwakawa, Tsuguchika Tabaru, Atsuki Inoue, Hiroshi Kawaguchi
Automatic Pruning Rate Derivation for Structured Pruning of Deep Neural Networks. ICPR 2022: 2561-2567 - [c124]Shintaro Izumi
Non-contact Atrial Fibrillation Detection using a 24-GHz Microwave Doppler Radar. IEEE SENSORS 2022: 1-4 - [c123]Ryo Takamatsu
Wearable Perspiration Volume Sensor Using Dual-Frequency Impedance Measurement. IEEE SENSORS 2022: 1-4 - [c122]Ryoto Yoshikura, Shintaro Izumi
Machine Learning-Based Severity Classification of Spinal Cord Injury Patients Using Straight Leg Raising Test. IEEE SENSORS 2022: 1-4 - 2021
- [j90]Toru Ishii
Subcentimeter Precision Ranging System for Moving Targets With a Doppler-Effect- Compensated Ultrasonic Direct Sequence Spread Spectrum. IEEE Trans. Instrum. Meas. 70: 1-8 (2021) - [c121]Satoki Tsuji, Hiroshi Kawaguchi, Atsuki Inoue, Yasufumi Sakai, Fuyuka Yamada:
Greedy Search Algorithm for Mixed Precision in Post-Training Quantization of Convolutional Neural Network Inspired by Submodular Optimization. ACML 2021: 886-901 - [c120]Yukiko Yoshikawa
12.5-m Distance Measurement in High-Interference Environment Using Ultrasonic Array Sensors. I2MTC 2021: 1-6 - [c119]Fuyuka Yamada, Satoki Tsuji, Hiroshi Kawaguchi
A High-Speed Neural Architecture Search Considering the Number of Weights. KI 2021: 109-115 - 2020
- [j89]Kento Watanabe
Heartbeat Interval Error Compensation Method for Low Sampling Rates Photoplethysmography Sensors. IEICE Trans. Commun. 103-B(6): 645-652 (2020) - [j88]Reiya Kawamoto
A 1.15-TOPS 6.57-TOPS/W Neural Network Processor for Multi-Scale Object Detection With Reduced Convolutional Operations. IEEE J. Sel. Top. Signal Process. 14(4): 634-645 (2020) - [c118]Reiya Kawamoto, Masakazu Taichi, Masaya Kabuto, Daisuke Watanabe, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A 1.15-TOPS 6.57-TOPS/W DNN Processor for Multi-Scale Object Detection. AICAS 2020: 203-207 - [c117]Daisuke Watanabe, Yuji Yano, Shintaro Izumi, Hiroshi Kawaguchi
An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing. AICAS 2020: 305-309 - [c116]Toru Ishii, Yukiko Yoshikawa, Shintaro Izumi, Hiroshi Kawaguchi
Doppler shift compensation technique for ultrasonic DSSS ranging system. I2MTC 2020: 1-6
2010 – 2019
- 2019
- [j87]Shintaro Izumi, Takaaki Okano, Daichi Matsunaga, Hiroshi Kawaguchi
Non-Contact Instantaneous Heart Rate Extraction System Using 24-GHz Microwave Doppler Sensor. IEICE Trans. Commun. 102-B(6): 1088-1096 (2019) - [j86]Kento Watanabe
Low-Noise Photoplethysmography Sensor Using Correlated Double Sampling for Heartbeat Interval Acquisition. IEEE Trans. Biomed. Circuits Syst. 13(6): 1552-1562 (2019) - [j85]Haruki Mori
A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(4): 1442-1453 (2019) - [j84]Seiya Yoshida
Energy-Efficient Spectral Analysis Method Using Autoregressive Model-Based Approach for Internet of Things. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(10): 3896-3905 (2019) - [j83]Takaaki Okano
Multimodal Cardiovascular Information Monitor Using Piezoelectric Transducers for Wearable Healthcare. J. Signal Process. Syst. 91(9): 1053-1062 (2019) - [c115]Yuji Yano, Seiya Yoshida, Shintaro Izumi, Hiroshi Kawaguchi
An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment. A-SSCC 2019: 267-270 - [c114]Seiya Yoshida, Shintaro Izumi, Yuki Nishikawa, Kento Watanabe, Kana Sasai, Yuji Yano, Hiroshi Kawaguchi
A Heartbeat Interval Error Compensation Method Using Multiple Linear Regression for Photoplethysmography Sensors. BioCAS 2019: 1-4 - [c113]Kana Sasai, Shintaro Izumi, Kento Watanabe, Yuji Yano, Hiroshi Kawaguchi
A Low-Power Photoplethysmography Sensor using Correlated Double Sampling and Reference Readout Circuit. IEEE SENSORS 2019: 1-4 - 2018
- [j82]Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi
A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video [IEICE Electronics Express Vol. 14(2017) No. 15 pp. 20170668]. IEICE Electron. Express 15(12): 20188003 (2018) - [j81]Motofumi Nakanishi, Shintaro Izumi, Mio Tsukahara, Hiroshi Kawaguchi
A 11.3-µA Physical Activity Monitoring System Using Acceleration and Heart Rate. IEICE Trans. Electron. 101-C(4): 233-242 (2018) - [c112]Tetsuya Youkawa, Haruki Mori, Yuki Miyauchi, Kazuki Yamada, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Delayed Weight Update for Faster Convergence in Data-Parallel Deep Learning. GlobalSIP 2018: 663-667 - [c111]Haruki Mori, Shintaro Izumi, Hiroshi Kawaguchi
28-nm FD-SOI Dual-Port SRAM with MSB-Based Inversion Logic for Low-Power Deep Learning. ICECS 2018: 161-164 - [c110]Yuki Miyauchi, Haruki Mori, Tetsuya Youkawa, Kazuki Yamada, Shintato Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Layer Skip Learning using LARS variables for 39% Faster Conversion Time and Lower Bandwidth. ICECS 2018: 673-676 - [c109]Yuki Nishikawa, Shintaro Izumi, Yuji Yano, Hiroshi Kawaguchi
Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring. ISCAS 2018: 1-5 - [c108]Kazuki Yamada, Haruki Mori, Tetsuya Youkawa, Yuki Miyauchi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Adaptive Learning Rate Adjustment with Short-Term Pre-Training in Data-Parallel Deep Learning. SiPS 2018: 100-105 - [c107]Koichi Kajihara, Shintaro Izumi, Seiya Yoshida, Yuji Yano, Hiroshi Kawaguchi
Hardware Implementation of Autoregressive Model Estimation Using Burg's Method for Low-Energy Spectral Analysis. SiPS 2018: 199-204 - 2017
- [j80]Go Matsukawa, Taisuke Kodama, Yuri Nishizumi, Koichi Kajihara, Chikako Nakanishi, Shintaro Izumi, Hiroshi Kawaguchi
A low power, VLSI object recognition processor using Sparse FIND feature for 60 fps HDTV resolution video. IEICE Electron. Express 14(15): 20170668 (2017) - [c106]Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi
A 19-μA metabolic equivalents monitoring SoC using adaptive sampling. ASP-DAC 2017: 37-38 - [c105]Takumi Katsuura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Wearable pulse wave velocity sensor using flexible piezoelectric film array. BioCAS 2017: 1-4 - [c104]Yuki Nagasato, Shintaro Izumi, Hiroshi Kawaguchi
Capacitively coupled ECG sensor system with digitally assisted noise cancellation for wearable application. BioCAS 2017: 1-4 - [c103]Takaaki Okano, Shintaro Izumi, Hiroshi Kawaguchi
Non-contact biometric identification and authentication using microwave Doppler sensor. BioCAS 2017: 1-4 - [c102]Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi
A swallowable sensing device platform with wireless power feeding and chemical reaction actuator. EMBC 2017: 3040-3043 - [c101]Haruki Mori, Tetsuya Youkawa, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A layer-block-wise pipeline for memory and bandwidth reduction in distributed deep learning. MLSP 2017: 1-6 - [c100]Yuri Nishizumi, Go Matsukawa, Koichi Kajihara, Taisuke Kodama, Shintaro Izumi, Hiroshi Kawaguchi
FPGA implementation of object recognition processor for HDTV resolution video using sparse FIND feature. SiPS 2017: 1-6 - [c99]Takaaki Okano, Shintaro Izumi, Takumi Katsuura, Hiroshi Kawaguchi
Multimodal cardiovascular information monitor using piezoelectric transducers for wearable healthcare. SiPS 2017: 1-6 - 2016
- [j79]Go Matsukawa, Yuta Kimi, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi
Error Propagation Analysis for Single Event Upset considering Masking Effects on Re-Convergent Path. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(6): 1198-1205 (2016) - [j78]Haruki Mori, Yohei Umeki, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi
A 28-nm 484-fJ/writecycle 650-fJ/readcycle 8T Three-Port FD-SOI SRAM for Image Processor. IEICE Trans. Electron. 99-C(8): 901-908 (2016) - [j77]Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. IPSJ Trans. Syst. LSI Des. Methodol. 9: 79-83 (2016) - [c98]Yuta Kawamoto, Shintaro Izumi, Yoshito Tanaka, Hiroshi Kawaguchi
Capacitively coupled ECG sensor using a single electrode with adaptive power-line noise cancellation. BHI 2016: 212-215 - [c97]Daichi Matsunaga, Shintaro Izumi, Hiroshi Kawaguchi
Non-contact Instantaneous Heart Rate Monitoring Using Microwave Doppler Sensor and Time-Frequency Domain Analysis. BIBE 2016: 172-175 - [c96]Yoshito Tanaka, Shintaro Izumi, Yuta Kawamoto, Hiroshi Kawaguchi
Adaptive noise cancellation method for capacitively coupled ECG sensor using single insulated electrode. BioCAS 2016: 296-299 - [c95]Mio Tsukahara, Motofumi Nakanishi, Shintaro Izumi, Yozaburo Nakai, Hiroshi Kawaguchi
Low-power metabolic equivalents estimation algorithm using adaptive acceleration sampling. EMBC 2016: 1878-1881 - [c94]Ryota Nakamura, Shintaro Izumi, Hiroshi Kawaguchi
Swallowable sensing device for long-term gastrointestinal tract monitoring. EMBC 2016: 3039-3042 - [c93]Mio Tsukahara, Shintaro Izumi, Motofumi Nakanishi, Hiroshi Kawaguchi
A 15-μA metabolic equivalents monitoring system using adaptive acceleration sampling and normally off computing. ICECS 2016: 61-64 - [c92]Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi
An low-energy 8T dual-port SRAM for image processor with selective sourceline drive scheme in 28-nm FD-SOI process technology. ICECS 2016: 532-535 - [c91]Shuhei Yoshida, Go Matsukawa, Shintaro Izumi, Hiroshi Kawaguchi
An soft error propagation analysis considering logical masking effect on re-convergent path. IOLTS 2016: 13-16 - 2015
- [j76]Go Matsukawa, Yohei Nakata, Yasuo Sugure, Shigeru Oho, Yuta Kimi, Masafumi Shimozawa, Shuhei Yoshida, Hiroshi Kawaguchi
A Low-Latency DMR Architecture with Fast Checkpoint Recovery Scheme. IEICE Trans. Electron. 98-C(4): 333-339 (2015) - [j75]Shintaro Izumi, Masanao Nakano, Ken Yamashita, Yozaburo Nakai, Hiroshi Kawaguchi
Noise Tolerant Heart Rate Extraction Algorithm Using Short-Term Autocorrelation for Wearable Healthcare Systems. IEICE Trans. Inf. Syst. 98-D(5): 1095-1103 (2015) - [j74]Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
An I/O-Sized ADC with Second-Order TDC and MOM Capacitor Voltage-to-Time Converter. IEICE Trans. Electron. 98-C(6): 489-495 (2015) - [j73]Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Low-Jitter Design for Second-Order Time-to-Digital Converter Using Frequency Shift Oscillators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(7): 1475-1481 (2015) - [j72]Keisuke Okuno, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi
A Fast Settling All Digital PLL Using Temperature Compensated Oscillator Tuning Word Estimation Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2592-2599 (2015) - [j71]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Shusuke Yoshimoto, Tomoki Nakagawa, Yozaburo Nakai, Hiroshi Kawaguchi
Normally Off ECG SoC With Non-Volatile MCU and Noise Tolerant Heartbeat Detector. IEEE Trans. Biomed. Circuits Syst. 9(5): 641-651 (2015) - [j70]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi
A Wearable Healthcare System With a 13.7 µ A Noise Tolerant ECG Processor. IEEE Trans. Biomed. Circuits Syst. 9(5): 733-742 (2015) - [c90]Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A negative-resistance sense amplifier for low-voltage operating STT-MRAM. ASP-DAC 2015: 8-9 - [c89]Yozaburo Nakai, Shintaro Izumi, Ken Yamashita, Masanao Nakano, Hiroshi Kawaguchi
A 14µA ECG processor with noise tolerant heart rate extractor and FeRAM for wearable healthcare systems. ASP-DAC 2015: 16-17 - [c88]Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi
Analysis of Soft Error Propagation Considering Masking Effects on Re-Convergent Path. ATS 2015: 139-144 - [c87]Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. CICC 2015: 1-4 - [c86]Motofumi Nakanishi, Shintaro Izumi, Sho Nagayoshi, Hironori Sato, Hiroshi Kawaguchi
Physical activity group classification algorithm using triaxial acceleration and heart rate. EMBC 2015: 510-513 - [c85]Taisuke Kodama, Shintaro Izumi, Kana Masaki, Hiroshi Kawaguchi
Large displacement haptic stimulus actuator using piezoelectric pump for wearable devices. EMBC 2015: 1172-1175 - [c84]Daichi Matsunaga, Shintaro Izumi, Keisuke Okuno, Hiroshi Kawaguchi
Non-contact and noise tolerant heart rate monitoring using microwave doppler sensor and range imagery. EMBC 2015: 6118-6121 - [c83]Yuta Kimi, Go Matsukawa, Shuhei Yoshida, Shintaro Izumi, Hiroshi Kawaguchi
An accurate soft error propagation analysis technique considering temporal masking disablement. IOLTS 2015: 23-25 - [c82]Tomoki Nakagawa, Shintaro Izumi, Koji Yanagida, Yuki Kitahara, Shusuke Yoshimoto, Yohei Umeki, Haruki Mori, Hiroto Kitahara, Hiroshi Kawaguchi
A low power 6T-4C non-volatile memory using charge sharing and non-precharge techniques. ISCAS 2015: 2904-2907 - [c81]Shintaro Izumi, Hiroshi Kawaguchi
A ferroelectric-based non-volatile flip-flop for wearable healthcare systems. NVMTS 2015: 1-4 - 2014
- [j69]Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi
A 54-mw 3×-real-time 60-kword continuous speech recognition processor VLSI. IEICE Electron. Express 11(2): 20130787 (2014) - [j68]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata
A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation. IEICE Trans. Electron. 97-C(4): 332-341 (2014) - [j67]Shusuke Yoshimoto
Soft-Error Resilient and Margin-Enhanced N-P Reversed 6T SRAM Bitcell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(9): 1945-1951 (2014) - [j66]Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
STT-MRAM Operating at 0.38V Using Negative-Resistance Sense Amplifier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2411-2417 (2014) - [j65]Kenta Takagi
A Real-time Scalable Object Detection System using Low-power HOG Accelerator VLSI. J. Signal Process. Syst. 76(3): 261-274 (2014) - [c80]Go Matsukawa, Yohei Nakata, Yuta Kimi, Yasuo Sugure, Masafumi Shimozawa, Shigeru Oho, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM. ARCS Workshops 2014: 1-5 - [c79]Shintaro Izumi, Hiroshi Kawaguchi
Normally-off technologies for healthcare appliance. ASP-DAC 2014: 17-20 - [c78]Hiromitsu Kimura, Takaaki Fuchikami, Kyoji Marumoto, Yoshikazu Fujimori, Shintaro Izumi, Hiroshi Kawaguchi
A 2.4 pJ ferroelectric-based non-volatile flip-flop with 10-year data retention capability. A-SSCC 2014: 21-24 - [c77]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Tomoki Nakagawa, Yuki Kitahara, Koji Yanagida, Shusuke Yoshimoto, Hiroshi Kawaguchi
A 6.14µA normally-off ECG-SoC with noise tolerant heart rate extractor for wearable healthcare systems. BioCAS 2014: 280-283 - [c76]Yozaburo Nakai, Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi
Noise tolerant QRS detection using template matching with short-term autocorrelation. EMBC 2014: 34-37 - [c75]Keisuke Okuno, Kana Masaki, Shintaro Izumi, Toshihiro Konishi, Hiroshi Kawaguchi
A 2.23 ps RMS jitter 3 μs fast settling ADPLL using temperature compensation PLL controller. ICECS 2014: 68-71 - [c74]Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
An 8-bit I/O-sized ADC with second-order TDC and MOM capacitor voltage-to-time converter. ICECS 2014: 223-226 - [c73]Tomoki Nakagawa, Shintaro Izumi, Shusuke Yoshimoto, Koji Yanagida, Yuki Kitahara, Hiroshi Kawaguchi
A 6T-4C shadow memory using plate line and word line boosting. ISCAS 2014: 2736-2739 - [c72]Yohei Nakata, Yuta Kimi, Shunsuke Okumura, Jinwook Jung, Takuya Sawada, Taku Toshikawa, Makoto Nagata
A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement. ISQED 2014: 16-23 - 2013
- [j64]Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
An Opampless Second-Order MASH ΔΣ ADC with Using Gated Ring Oscillator Time-to-Digital Converter. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(2): 434-442 (2013) - [j63]Kosuke Mizuno, Kenta Takagi
A Sub-100 mW Dual-Core HOG Accelerator VLSI for Parallel Feature Extraction Processing for HDTV Resolution Video. IEICE Trans. Electron. 96-C(4): 433-443 (2013) - [j62]Guangji He, Takanobu Sugahara, Yuki Miyamoto, Shintaro Izumi, Hiroshi Kawaguchi
A 168-mW 2.4X-Real-Time 60-kWord Continuous Speech Recognition Processor VLSI. IEICE Trans. Electron. 96-C(4): 444-453 (2013) - [j61]Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi
Reconfiguring Cache Associativity: Adaptive Cache Design for Wide-Range Reliable Low-Voltage Operation Using 7T/14T SRAM. IEICE Trans. Electron. 96-C(4): 528-537 (2013) - [j60]Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A Second-Order All-Digital TDC with Low-Jitter Frequency Shift Oscillators and Dynamic Flipflops. IEICE Trans. Electron. 96-C(4): 546-552 (2013) - [j59]Shusuke Yoshimoto, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi
Multiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(7): 1579-1585 (2013) - [j58]Kosuke Mizuno, Yosuke Terachi, Kenta Takagi
An FPGA Implementation of a HOG-based Object Detection Processor. IPSJ Trans. Syst. LSI Des. Methodol. 6: 42-51 (2013) - [c71]Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi
A 40-nm 144-mW VLSI processor for real-time 60-kWord continuous speech recognition. ASP-DAC 2013: 71-72 - [c70]Shusuke Yoshimoto, Masaharu Terada, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM using low-power disturb mitigation technique. ASP-DAC 2013: 77-78 - [c69]Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi
A physical unclonable function chip exploiting load transistors' variation in SRAM bitcells. ASP-DAC 2013: 79-80 - [c68]Shintaro Izumi, Masanao Nakano, Ken Yamashita, Takahide Fujii, Hiroshi Kawaguchi
Low-power hardware implementation of noise tolerant heart rate extractor for a wearable monitoring system. BIBE 2013: 1-4 - [c67]Shusuke Yoshimoto, Shinji Miyano, Makoto Takamiya, Hirofumi Shinohara, Hiroshi Kawaguchi
A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure. CICC 2013: 1-4 - [c66]Takahide Fujii, Masanao Nakano, Ken Yamashita, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi
Noise-tolerant instantaneous heart rate and R-peak detection using short-term autocorrelation for wearable healthcare systems. EMBC 2013: 7330-7333 - [c65]Shintaro Izumi, Ken Yamashita, Masanao Nakano, Toshihiro Konishi, Hiroshi Kawaguchi
A 14 µA ECG processor with robust heart rate monitor for a wearable healthcare system. ESSCIRC 2013: 145-148 - [c64]Kenta Takagi
A sub-100-milliwatt dual-core HOG accelerator VLSI for real-time multiple object detection. ICASSP 2013: 2533-2537 - [c63]Jinwook Jung, Yohei Nakata, Masahiko Yoshimoto, Hiroshi Kawaguchi
Energy-efficient Spin-Transfer Torque RAM cache exploiting additional all-zero-data flags. ISQED 2013: 216-222 - [c62]Keisuke Okuno, Shintaro Izumi, Toshihiro Konishi, Song Dae-Woo, Masahiko Yoshimoto, Hiroshi Kawaguchi
Temperature compensation using least mean squares for fast settling all-digital phase-locked loop. NEWCAS 2013: 1-4 - [c61]Ken Yamashita, Shintaro Izumi, Masanao Nakano, Takahide Fujii, Toshihiro Konishi, Hiroshi Kawaguchi
A 38 μA wearable biosignal monitoring system with near field communication. NEWCAS 2013: 1-4 - [c60]Guangji He, Yuki Miyamoto, Kumpei Matsuda, Shintaro Izumi, Hiroshi Kawaguchi
A 40-NM 54-MW 3×-real-time VLSI processor for 60-kWord continuous speech recognition. SiPS 2013: 147-152 - 2012
- [j57]Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi
Low-energy block-level instantaneous comparison 7T SRAM for dual modular redundancy. IEICE Electron. Express 9(6): 470-476 (2012) - [j56]Shusuke Yoshimoto
A 40-nm 256-Kb Half-Select Resilient 8T SRAM with Sequential Writing Technique. IEICE Electron. Express 9(12): 1023-1029 (2012) - [j55]Takashi Matsuda, Shintaro Izumi, Yasuharu Sakai, Takashi Takeuchi, Hidehiro Fujiwara, Hiroshi Kawaguchi
Divided Static Random Access Memory for Data Aggregation in Wireless Sensor Nodes. IEICE Trans. Commun. 95-B(1): 178-188 (2012) - [j54]Yohei Nakata, Hiroshi Kawaguchi
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers and Variable-Cycle Pipeline Adaptive Routing. IEICE Trans. Electron. 95-C(4): 523-533 (2012) - [j53]Shusuke Yoshimoto
A 40-nm 0.5-V 12.9-pJ/Access 8T SRAM Using Low-Energy Disturb Mitigation Scheme. IEICE Trans. Electron. 95-C(4): 572-578 (2012) - [j52]Shunsuke Okumura, Hidehiro Fujiwara, Kosuke Yamaguchi, Shusuke Yoshimoto, Masahiko Yoshimoto, Hiroshi Kawaguchi
A 0.15-µm FD-SOI Substrate Bias Control SRAM with Inter-Die Variability Compensation Scheme. IEICE Trans. Electron. 95-C(4): 579-585 (2012) - [j51]Shusuke Yoshimoto
Bit-Error and Soft-Error Resilient 7T/14T SRAM with 150-nm FD-SOI Process. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(8): 1359-1365 (2012) - [j50]Shusuke Yoshimoto, Takuro Amashita, Shunsuke Okumura, Hiroshi Kawaguchi
Multiple-Bit-Upset and Single-Bit-Upset Resilient 8T SRAM Bitcell Layout with Divided Wordline Structure. IEICE Trans. Electron. 95-C(10): 1675-1681 (2012) - [j49]Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi
A 128-bit Chip Identification Generating Scheme Exploiting Load Transistors' Variation in SRAM Bitcells. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 95-A(12): 2226-2233 (2012) - [j48]Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi, Masahiko Yoshimoto:
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. Inf. Media Technol. 7(2): 544-555 (2012) - [j47]Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi
0.5-V 4-MB Variation-Aware Cache Architecture Using 7T/14T SRAM and Its Testing Scheme. IPSJ Trans. Syst. LSI Des. Methodol. 5: 32-43 (2012) - [j46]Guangji He, Takanobu Sugahara, Yuki Miyamoto, Tsuyoshi Fujinaga, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi
A 40 nm 144 mW VLSI Processor for Real-Time 60-kWord Continuous Speech Recognition. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(8): 1656-1666 (2012) - [c59]Shinpei Soda, Masahide Nakamura
Implementing Virtual Agent as an Interface for Smart Home Voice Control. APSEC 2012: 342-345 - [c58]Koji Kugata, Shinpei Soda, Yohei Nakata, Shunsuke Okumura, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Processor Coupling Architecture for Aggressive Voltage Scaling on Multicores. ARCS Workshops 2012: 375-384 - [c57]Guangji He, Takanobu Sugahara, Shintaro Izumi, Hiroshi Kawaguchi
A 40-nm 168-mW 2.4×-real-time VLSI processor for 60-kWord continuous speech recognition. CICC 2012: 1-4 - [c56]Masanao Nakano, Toshihiro Konishi, Shintaro Izumi, Hiroshi Kawaguchi
Instantaneous Heart Rate detection using short-time autocorrelation for wearable healthcare systems. EMBC 2012: 6703-6706 - [c55]Shinpei Soda, Masahide Nakamura
Handsfree Voice Interface for Home Network Service Using a Microphone Array Network. ICNC 2012: 195-200 - [c54]Shusuke Yoshimoto, Takuro Amashita, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura
Neutron-induced soft error rate estimation for SRAM using PHITS. IOLTS 2012: 138-141 - [c53]Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A 51-dB SNDR DCO-based TDC using two-stage second-order noise shaping. ISCAS 2012: 3170-3173 - [c52]Shusuke Yoshimoto, Masaharu Terada, Youhei Umeki, Shunsuke Okumura, Atsushi Kawasumi, Toshikazu Suzuki, Shinichi Moriwaki, Shinji Miyano, Hiroshi Kawaguchi
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme. ISLPED 2012: 85-90 - [c51]Masaharu Terada, Shusuke Yoshimoto, Shunsuke Okumura, Toshikazu Suzuki, Shinji Miyano, Hiroshi Kawaguchi
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction. ISQED 2012: 489-492 - [c50]Yuki Kagiyama, Shunsuke Okumura, Koji Yanagida, Shusuke Yoshimoto, Yohei Nakata, Shintaro Izumi, Hiroshi Kawaguchi
Bit error rate estimation in SRAM considering temperature fluctuation. ISQED 2012: 516-519 - [c49]Keisuke Okuno, Toshihiro Konishi, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A 62-dB SNDR second-order gated ring oscillator TDC with two-stage dynamic D-type flipflops as a quantization noise propagator. NEWCAS 2012: 289-292 - [c48]Kosuke Mizuno, Yosuke Terachi, Kenta Takagi
Architectural Study of HOG Feature Extraction Processor for Real-Time Object Detection. SiPS 2012: 197-202 - [c47]Toshihiro Konishi, Keisuke Okuno, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops. VLSIC 2012: 190-191 - 2011
- [j45]Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Tsuyoshi Fujinaga, Shintaro Izumi, Yasuo Ariki, Hiroshi Kawaguchi
A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition. IEICE Trans. Electron. 94-C(4): 448-457 (2011) - [j44]Hiroki Noguchi, Kazuo Miura, Tsuyoshi Fujinaga, Takanobu Sugahara, Hiroshi Kawaguchi
VLSI Architecture of GMM Processing and Viterbi Decoder for 60, 000-Word Real-Time Continuous Speech Recognition. IEICE Trans. Electron. 94-C(4): 458-467 (2011) - [j43]Toshihiro Konishi, Shintaro Izumi, Koh Tsuruda, Hyeokjong Lee, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A Low-Power Multi Resolution Spectrum Sensing Architecture for a Wireless Sensor Network with Cognitive Radio. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(11): 2287-2294 (2011) - [j42]Shunsuke Okumura, Yuki Kagiyama, Yohei Nakata, Shusuke Yoshimoto, Hiroshi Kawaguchi
7T SRAM Enabling Low-Energy Instantaneous Block Copy and Its Application to Transactional Memory. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2693-2700 (2011) - [j41]Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Takashi Takeuchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A Low-Power Multi-Phase Oscillator with Transfer Gate Phase Coupler Enabling Even-Numbered Phase Output. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2701-2708 (2011) - [j40]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. Inf. Media Technol. 6(2): 296-306 (2011) - [j39]Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi:
Data-Intensive Sound Acquisition System with Large-scale Microphone Array. Inf. Media Technol. 6(2): 307-318 (2011) - [j38]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Koji Nii, Hiroshi Kawaguchi
Design Choice in 45-nm Dual-Port SRAM - 8T, 10T Single End, and 10T Differential. IPSJ Trans. Syst. LSI Des. Methodol. 4: 80-90 (2011) - [j37]Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Data-Intensive Sound Acquisition System with Large-scale Microphone Array. J. Inf. Process. 19: 129-140 (2011) - [c46]Guangji He, Takanobu Sugahara, Tsuyoshi Fujinaga, Yuki Miyamoto, Hiroki Noguchi, Shintaro Izumi, Hiroshi Kawaguchi
A 40 nm 144 mW VLSI processor for realtime 60 kWord continuous speech recognition. CICC 2011: 1-4 - [c45]Shunsuke Okumura, Yohei Nakata, Koji Yanagida, Yuki Kagiyama, Shusuke Yoshimoto, Hiroshi Kawaguchi
Low-power block-level instantaneous comparison 7T SRAM for dual modular redundancy. CICC 2011: 1-4 - [c44]Yohei Nakata, Yukihiro Takeuchi, Hiroshi Kawaguchi
A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers. DSD 2011: 801-804 - [c43]Yohei Nakata, Yasuhiro Ito, Yasuo Sugure, Shigeru Oho, Yusuke Takeuchi, Shunsuke Okumura, Hiroshi Kawaguchi
Model-based fault injection for failure effect analysis - Evaluation of dependable SRAM for vehicle control units. DSN Workshops 2011: 91-96 - [c42]Shunsuke Okumura, Shusuke Yoshimoto, Hiroshi Kawaguchi
A 128-bit chip identification generating scheme exploiting SRAM bitcells with failure rate of 4.45 × 10-19. ESSCIRC 2011: 527-530 - [c41]Shintaro Izumi, Hiroki Noguchi, Tomoya Takagi, Koji Kugata, Shinpei Soda, Masahiko Yoshimoto, Hiroshi Kawaguchi
Data Aggregation Protocol for Multiple Sound Sources Acquisition with Microphone Array Network. ICCCN 2011: 1-6 - [c40]Jinwook Jung, Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi
256-KB associativity-reconfigurable cache with 7T/14T SRAM for aggressive DVS down to 0.57 V. ICECS 2011: 524-527 - [c39]Shusuke Yoshimoto, Takuro Amashita, D. Kozuwa, Taiga Takata, Masayoshi Yoshimura, Yusuke Matsunaga, Hiroto Yasuura
Multiple-bit-upset and single-bit-upset resilient 8T SRAM bitcell layout with divided wordline structure. IOLTS 2011: 151-156 - [c38]Toshihiro Konishi, Hyeokjong Lee, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi
A 40-nm 640-µm2 45-dB opampless all-digital second-order MASH ΔΣ ADC. ISCAS 2011: 518-521 - [c37]Hiroki Noguchi, Shunsuke Okumura, Tomoya Takagi, Koji Kugata, Masahiko Yoshimoto, Hiroshi Kawaguchi
0.45-V operating Vt-variation tolerant 9T/18T dual-port SRAM. ISQED 2011: 219-222 - [c36]Masahiro Yoshikawa, Shunsuke Okumura, Yohei Nakata, Yuki Kagiyama, Hiroshi Kawaguchi
Block-basis on-line BIST architecture for embedded SRAM using wordline and bitcell voltage optimal control. ISQED 2011: 322-325 - 2010
- [j36]Takashi Matsuda, Takashi Takeuchi, Takefumi Aonishi, Masumi Ichien, Hiroshi Kawaguchi
A power-variation model for sensor node and the impact against life time of wireless sensor networks. IEICE Electron. Express 7(3): 197-202 (2010) - [j35]Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hyeokjong Lee, Toshihiro Konishi, Koh Tsuruda, Yasuharu Sakai, Hiroshi Kawaguchi
A 58-µW Single-Chip Sensor Node Processor with Communication Centric Design. IEICE Trans. Electron. 93-C(3): 261-269 (2010) - [c35]Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Masanori Nishino, Shintaro Izumi, Hiroshi Kawaguchi
A 34.7-mW quad-core MIQP solver processor for robot control. CICC 2010: 1-4 - [c34]Shunsuke Okumura, Shusuke Yoshimoto, Kosuke Yamaguchi, Yohei Nakata, Hiroshi Kawaguchi
7T SRAM enabling low-energy simultaneous block copy. CICC 2010: 1-4 - [c33]Kosuke Mizuno, Hiroki Noguchi, Guangji He, Yosuke Terachi, Tetsuya Kamino, Hiroshi Kawaguchi
Fast and Low-Memory-Bandwidth Architecture of SIFT Descriptor Generation with Scalability on Speed and Accuracy for VGA Video. FPL 2010: 608-611 - [c32]Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Live demonstration: Intelligent ubiquitous sensor network for sound acquisition. ISCAS 2010: 1413 - [c31]Koji Kugata, Tomoya Takagi, Hiroki Noguchi, Masahiko Yoshimoto, Hiroshi Kawaguchi
Intelligent ubiquitous sensor network for sound acquisition. ISCAS 2010: 1414-1417 - [c30]Hiroki Noguchi, Junichi Tani, Yusuke Shimai, Hiroshi Kawaguchi
Parallel-processing VLSI architecture for mixed integer linear programming. ISCAS 2010: 2362-2365 - [c29]Yohei Nakata, Shunsuke Okumura, Hiroshi Kawaguchi
0.5-V operation variation-aware word-enhancing cache architecture using 7T/14T hybrid SRAM. ISLPED 2010: 219-224
2000 – 2009
- 2009
- [j34]Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi
A Dependable SRAM with 7T/14T Memory Cells. IEICE Trans. Electron. 92-C(4): 423-432 (2009) - [j33]Takashi Takeuchi, Shinji Mikami, Hyeokjong Lee, Hiroshi Kawaguchi
A 433-MHz Rail-to-Rail Voltage Amplifier with Carrier Sensing Function for Wireless Sensor Networks. IEICE Trans. Electron. 92-C(6): 815-821 (2009) - [c28]Hiroshi Kawaguchi
Low-power control techniques for silicon and organic circuits with array structures. CCA/ISIC 2009: 326-333 - [c27]Tsuyoshi Fujinaga, Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi
Parallelized viterbi processor for 5, 000-word large-vocabulary real-time continuous speech recognition FPGA system. INTERSPEECH 2009: 1483-1486 - [c26]Shunsuke Okumura, Yusuke Iguchi, Shusuke Yoshimoto, Hidehiro Fujiwara, Hiroki Noguchi, Koji Nii, Hiroshi Kawaguchi
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. ISQED 2009: 659-663 - [c25]Hiroki Noguchi, Tomoya Takagi, Masahiko Yoshimoto, Hiroshi Kawaguchi
An ultra-low-power VAD hardware implementation for intelligent ubiquitous sensor networks. SiPS 2009: 214-219 - [c24]Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Hiroshi Kawaguchi
A 7T/14T Dependable SRAM and its Array Structure to Avoid Half Selection. VLSI Design 2009: 295-300 - 2008
- [j32]Yuichiro Murachi, Yuki Fukuyama, Ryo Yamamoto, Junichi Miyakoshi, Hiroshi Kawaguchi
A VGA 30-fps Realtime Optical-Flow Processor Core for Moving Picture Recognition. IEICE Trans. Electron. 91-C(4): 457-464 (2008) - [j31]Yuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi
A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer. IEICE Trans. Electron. 91-C(4): 465-478 (2008) - [j30]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Shunsuke Okumura, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi
A 10T Non-precharge Two-Port SRAM Reducing Readout Power for Video Processing. IEICE Trans. Electron. 91-C(4): 543-552 (2008) - [j29]Takashi Takeuchi, Yu Otake, Masumi Ichien, Akihiro Gion, Hiroshi Kawaguchi
Cross-Layer Design for Low-Power Wireless Sensor Node Using Wave Clock. IEICE Trans. Commun. 91-B(11): 3480-3488 (2008) - [j28]Shintaro Izumi, Takashi Takeuchi, Takashi Matsuda, Hiroshi Kawaguchi
Counter-Based Broadcasting with Hop Count Aware Random Assessment Delay Extension for Wireless Sensor Networks. IEICE Trans. Commun. 91-B(11): 3489-3498 (2008) - [j27]Hidehiro Fujiwara, Koji Nii, Hiroki Noguchi, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi
Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 620-627 (2008) - [c23]Kazuo Miura, Hiroki Noguchi, Hiroshi Kawaguchi
A low memory bandwidth Gaussian mixture model (GMM) processor for 20, 000-word real-time speech recognition FPGA system. FPT 2008: 341-344 - [c22]Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi
An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding. ICECS 2008: 1179-1182 - [c21]Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi
A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding. ISCAS 2008: 848-851 - [c20]Hidehiro Fujiwara, Shunsuke Okumura, Yusuke Iguchi, Hiroki Noguchi, Yasuhiro Morita, Hiroshi Kawaguchi
Quality of a Bit (QoB): A New Concept in Dependable SRAM. ISQED 2008: 98-102 - 2007
- [j26]Fayez Robert Saliba, Hiroshi Kawaguchi
A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's. IEICE Trans. Electron. 90-C(4): 743-748 (2007) - [j25]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes. IEICE Trans. Electron. 90-C(10): 1949-1956 (2007) - [j24]Hiroshi Kawaguchi
Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2669-2681 (2007) - [j23]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi
Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2695-2702 (2007) - [j22]Takashi Matsuda, Masumi Ichien, Hiroshi Kawaguchi
Data Transmission Scheduling Based on RTS/CTS Exchange for Periodic Data Gathering Sensor Networks. IEICE Trans. Commun. 90-B(12): 3410-3418 (2007) - [j21]Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi
An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display. IEEE J. Solid State Circuits 42(1): 93-100 (2007) - [j20]Kohei Onizuka, Kenichi Inagaki, Hiroshi Kawaguchi
Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs. IEEE J. Solid State Circuits 42(11): 2404-2410 (2007) - [c19]Kentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi
Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline Architecture. ASP-DAC 2007: 292-297 - [c18]David Levacq, Muhammad Yazid, Hiroshi Kawaguchi
Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution. ESSCIRC 2007: 190-193 - [c17]Makoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi
Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches. ISSCC 2007: 362-609 - [c16]Hiroki Noguchi, Yusuke Iguchi, Hidehiro Fujiwara, Yasuhiro Morita, Koji Nii, Hiroshi Kawaguchi
A 10T Non-Precharge Two-Port SRAM for 74% Power Reduction in Video Processing. ISVLSI 2007: 107-112 - [c15]Takashi Matsuda, Takafumi Aonishi, Takashi Takeuchi, Hiroshi Kawaguchi
Multipath Routing using Isochronous Medium Access Control with Multi Wakeup Period for Wireless Sensor Networks. ISWCS 2007: 718-721 - 2006
- [j19]Canh Quang Tran, Hiroshi Kawaguchi
Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping. IEICE Trans. Electron. 89-C(3): 280-286 (2006) - [j18]Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi
Trends of On-Chip Interconnects in Deep Sub-Micron VLSI. IEICE Trans. Electron. 89-C(3): 392-394 (2006) - [j17]Shinji Mikami, Takafumi Aonishi, Hironori Yoshino, Chikara Ohta, Hiroshi Kawaguchi
Aggregation Efficiency-Aware Greedy Incremental Tree Routing for Wireless Sensor Networks. IEICE Trans. Commun. 89-B(10): 2741-2751 (2006) - [j16]Junichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi
A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing. IEICE Trans. Electron. 89-C(11): 1629-1636 (2006) - [j15]Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi
Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3569-3578 (2006) - [j14]Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3623-3633 (2006) - [j13]Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Kentaro Kawakami, Junichi Miyakoshi, Shinji Mikami, Koji Nii, Hiroshi Kawaguchi
A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3634-3641 (2006) - [j12]Kentaro Kawakami, Jun Takemura, Mitsuhiko Kuroda, Hiroshi Kawaguchi
A 50% Power Reduction in H.264/AVC HDTV Video Decoder LSI by Dynamic Voltage Scaling in Elastic Pipeline. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3642-3651 (2006) - [j11]Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi
Managing subthreshold leakage in charge-based analog circuits with low-VTH transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS). IEEE J. Solid State Circuits 41(4): 859-867 (2006) - [j10]Kohei Onizuka, Hiroshi Kawaguchi
$V_rm DD$-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time. IEEE J. Solid State Circuits 41(11): 2382-2389 (2006) - [j9]Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi
Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD LSIs. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 430-435 (2006) - [c14]Kohei Onizuka, Hiroshi Kawaguchi
Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications. CICC 2006: 575-578 - [c13]Takafumi Aonishi, Takashi Matsuda, Shinji Mikami, Hiroshi Kawaguchi
Impact of Aggregation Efficiency on GIT Routing forWireless Sensor Networks. ICPP Workshops 2006: 151-158 - [c12]Hidehiro Fujiwara, Koji Nii, Junichi Miyakoshi, Yuichiro Murachi, Yasuhiro Morita, Hiroshi Kawaguchi
A two-port SRAM for real-time video processor saving 53% of bitline power with majority logic and data-bit reordering. ISLPED 2006: 61-66 - [c11]Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi
An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin. ISSCC 2006: 1060-1069 - [c10]Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. VLSI-SoC 2006: 192-197 - 2005
- [j8]Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi
Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's. IEICE Trans. Electron. 88-C(4): 760-767 (2005) - [j7]Hiroshi Kawaguchi
Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin. IEEE J. Solid State Circuits 40(1): 177-185 (2005) - [j6]Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi
Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. Syst. Comput. Jpn. 36(6): 39-48 (2005) - [j5]Hiroshi Kawaguchi
μITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications. IEEE Trans. Multim. 7(1): 67-74 (2005) - [c9]Koichi Ishida, Kouichi Kanda, Atit Tamtrakarn, Hiroshi Kawaguchi
Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS). ISCAS (4) 2005: 3119-3122 - [c8]Canh Quang Tran, Hiroshi Kawaguchi
More than two orders of magnitude leakage current reduction in look-up table for FPGAs. ISCAS (5) 2005: 4701-4704 - 2004
- [c7]Takayuki Miyazaki, Canh Quang Tran, Hiroshi Kawaguchi
Observation of one-fifth-of-a-clock wake-up time of power-gated circuit. CICC 2004: 87-90 - 2002
- [j4]Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi
VTH-hopping scheme to reduce subthreshold leakage for low-power processors. IEEE J. Solid State Circuits 37(3): 413-419 (2002) - 2001
- [j3]Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi
Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs. IEEE J. Solid State Circuits 36(10): 1559-1564 (2001) - [c6]Koichi Nose, Masayuki Hirabayashi, Hiroshi Kawaguchi
VTH-hopping scheme for 82% power saving in low-voltage processors. CICC 2001: 93-96 - [c5]Youngsoo Shin, Hiroshi Kawaguchi
Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems. CICC 2001: 553-556 - [c4]Hiroshi Kawaguchi
An LSI for VDD-hopping and MPEG4 system based on the chip. ISCAS (4) 2001: 918-921 - 2000
- [j2]Hiroshi Kawaguchi
A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current. IEEE J. Solid State Circuits 35(10): 1498-1501 (2000) - [c3]Takashi Inukai, Makoto Takamiya, Kouichi Nose, Hiroshi Kawaguchi
Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration. CICC 2000: 409-412
1990 – 1999
- 1999
- [c2]Kouichi Kanda, Kouichi Nose, Hiroshi Kawaguchi, Takayasu Sakurai:
Design impact of positive temperature dependence of drain current in sub 1 V CMOS VLSIs. CICC 1999: 563-566 - 1998
- [j1]Hiroshi Kawaguchi
A reduced clock-swing flip-flop (RCSFF) for 63% power reduction. IEEE J. Solid State Circuits 33(5): 807-811 (1998) - [c1]Hiroshi Kawaguchi
Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. ASP-DAC 1998: 35-43
Coauthor Index
[j92] [j91] [c137] [c136] [c135] [c133] [c131] [c130] [c127] [c124] [c123] [c122] [j90] [c120] [j89] [j88] [c118] [c117] [c116] [j87] [j86] [j85] [j84] [j83] [c115] [c114] [c113] [j82] [j81] [c112] [c111] [c109] [c108] [c107] [j80] [c106] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [j79] [j78] [j77] [c98] [c97] [c96] [c95] [c94] [c93] [c92] [c91] [j75] [j74] [j73] [j72] [j71] [j70] [c90] [c89] [c88] [c87] [c86] [c85] [c84] [c83] [c82] [c81] [j69] [j66] [j65] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [j64] [j63] [j62] [j60] [j58] [c71] [c68] [c66] [c65] [c64] [c62] [c61] [c60] [j55] [j46] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c50] [c49] [c48] [c47] [j45] [j43] [j41] [j39] [j37] [c46] [c41] [c38] [j35] [c35] [j28]
[j89] [j88] [c118] [c117] [j87] [j86] [j85] [j84] [j83] [c115] [c114] [c113] [j82] [j81] [c112] [c111] [c110] [c109] [c108] [c107] [j80] [c106] [c105] [c104] [c103] [c102] [c101] [c100] [c99] [j79] [j78] [j77] [c98] [c97] [c96] [c95] [c94] [c93] [c92] [c91] [j76] [j75] [j74] [j73] [j72] [j71] [j70] [c90] [c89] [c88] [c87] [c86] [c85] [c84] [c83] [c82] [c81] [j69] [j68] [j67] [j66] [j65] [c80] [c79] [c78] [c77] [c76] [c75] [c74] [c73] [c72] [j64] [j63] [j62] [j61] [j60] [j59] [j58] [c71] [c70] [c69] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [c60] [j57] [j56] [j55] [j54] [j53] [j52] [j51] [j50] [j49] [j48] [j47] [j46] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [j45] [j44] [j43] [j42] [j41] [j40] [j39] [j38] [j37] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [j36] [j35] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [j34] [j33] [c27] [c26] [c25] [c24] [j32] [j31] [j30] [j29] [j28] [j27] [c23] [c22] [c21] [c20] [j25] [j23] [j22] [c19] [c16] [c15] [j17] [j16] [j14] [j13] [j12] [c13] [c12] [c10]
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