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Chih-Ting Yeh
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2020 – today
- 2023
- [c10]Chia-Ying Tsao, Chih-Ting Yeh, Jyh-Shing Roger Jang, Yung-Yaw Chen, Chuan-Ju Wang:
Multi-behavior Recommendation with Action Pattern-aware Networks. WI/IAT 2023: 16-23 - 2021
- [c9]Jia-Huei Ju, Chih-Ting Yeh, Cheng-Wei Lin, Chia-Ying Tsao, Jun-En Ding, Chuan-Ju Wang, Ming-Feng Tsai:
An Exploration Study of Multi-stage Conversational Passage Retrieval: Paraphrase Query Expansion and Multi-view Point-wise Ranking. TREC 2021 - [c8]Chih-Ting Yeh, Zhe-Li Lin, Sheng-Chieh Lin, Jing-Kai Lou, Ming-Feng Tsai, Chuan-Ju Wang:
A Learning Framework with Disposable Auxiliary Networks for Early Prediction of Product Success. WI/IAT 2021: 186-193
2010 – 2019
- 2019
- [c7]Chia-Ping Chen, Su-Yu Zhang, Chih-Ting Yeh, Jia-Ching Wang, Tenghui Wang, Chien-Lin Huang:
Speaker Characterization Using TDNN-LSTM Based Speaker Embedding. ICASSP 2019: 6211-6215 - [c6]Chih-Ting Yeh, Po-Chin Wang, Su-Yu Zhang, Chia-Ping Chen, Shan-Wen Hsiao, Bo-Cheng Chan, Chung-Li Lu:
以三元組損失微調時延神經網路語者嵌入函數之語者辨識系統(Time Delay Neural Network-based Speaker Embedding Function Fine-tuned with Triplet Loss for Distance-based Speaker Recognition). ROCLING 2019: 310-324 - 2018
- [c5]Chih-Ting Yeh, Chia-Ping Chen:
結合卷積神經網路與遞迴神經網路於推文極性分類 (Combining Convolutional Neural Network and Recurrent Neural Network for Tweet Polarity Classification) [In Chinese]. ROCLING 2018: 236-245 - 2013
- [j4]Chih-Ting Yeh, Ming-Dou Ker:
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit. Microelectron. Reliab. 53(2): 208-214 (2013) - [c4]Chih-Ting Yeh, Ming-Dou Ker:
Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process. VLSI-DAT 2013: 1-4 - 2012
- [j3]Chih-Ting Yeh, Ming-Dou Ker:
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications. Microelectron. Reliab. 52(6): 1020-1030 (2012) - [j2]Chih-Ting Yeh, Ming-Dou Ker:
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology. IEEE Trans. Circuits Syst. II Express Briefs 59-II(3): 178-182 (2012) - [c3]Chih-Ting Yeh, Ming-Dou Ker:
New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process. VLSI-DAT 2012: 1-4 - 2011
- [c2]Chih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker:
Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events. ISCAS 2011: 1403-1406 - 2010
- [j1]Chih-Ting Yeh, Ming-Dou Ker:
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection. IEEE J. Solid State Circuits 45(11): 2476-2486 (2010)
2000 – 2009
- 2008
- [c1]Shih-Hung Chen, Chih-Ting Yeh:
Active ESD protection design against cross-power-domain ESD stresses in CMOS integrated circuits. APCCAS 2008: 57-60
Coauthor Index
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