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Zhong Wang 0004
Person information
- affiliation (PhD 2007): University of Notre Dame, Department of Computer Science and Engineering, Notre Dame IN, USA
Other persons with the same name
- Zhong Wang — disambiguation page
- Zhong Wang 0001 — Dalian University of Technology, School of Software Technology, Dalian, China (and 4 more)
- Zhong Wang 0002
— Northwestern Polytechnical University, Department of Navigation, Guidance, and Control, Xi'an, China (and 1 more)
- Zhong Wang 0003
- Zhong Wang 0005
- Zhong Wang 0006
- Zhong Wang 0007
- Zhong Wang 0008
- Zhong Wang 0009
- Zhong Wang 0010
- Zhong Wang 0011
- Zhong Wang 0012
- Zhong Wang 0013
- Zhong Wang 0014
- Zhong Wang 0015
- Zhong Wang 0016 — Tianjin University, School of Precision Instrument and Opto-Electronics Engineering, State Key Laboratory of Precision Measuring Technology and Instrument, Tianjin, China
- Zhong Wang 0017 — PLA University of Science and Technology, Institute of Sciences, Nanjing, China
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2000 – 2009
- 2005
- [j4]Zhong Wang, Xiaobo Sharon Hu
Energy-aware variable partitioning and instruction scheduling for multibank memory architectures. ACM Trans. Design Autom. Electr. Syst. 10(2): 369-388 (2005) - 2004
- [c6]Zhong Wang, Xiaobo Sharon Hu
Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks. DATE 2004: 312-317 - 2003
- [c5]Zhong Wang, Xiaobo Sharon Hu, Edwin Hsing-Mean Sha:
Register aware scheduling for distributed cache clustered architecture. ASP-DAC 2003: 71-76 - 2002
- [j3]Zhong Wang, Edwin Hsing-Mean Sha, Yuke Wang:
Partitioning and Scheduling DSP Applications with Maximal Memory Access Hiding. EURASIP J. Adv. Signal Process. 2002(9): 926-935 (2002) - 2001
- [j2]Zhong Wang, Timothy W. O'Neil, Edwin Hsing-Mean Sha:
Optimal loop scheduling for hiding memory latency based on two-level partitioning and prefetching. IEEE Trans. Signal Process. 49(11): 2853-2864 (2001) - [j1]Zhong Wang, Timothy W. O'Neil, Edwin Hsing-Mean Sha:
Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and Prefetching. J. VLSI Signal Process. 27(3): 215-233 (2001) - [c4]Zhong Wang, Edwin Hsing-Mean Sha, Xiaobo Hu
Combined partitioning and data padding for scheduling multiple loop nests. CASES 2001: 67-75 - [c3]Zhong Wang, Edwin Hsing-Mean Sha, Yuke Wang:
Optimal partitioning and balanced scheduling with the maximal overlap of data footprints. ACM Great Lakes Symposium on VLSI 2001: 31-36 - [c2]Zhong Wang, Qingfeng Zhuge, Edwin Hsing-Mean Sha:
Scheduling and partitioning for multiple loop nests. ISSS 2001: 183-188 - 2000
- [c1]Zhong Wang, Michael Kirkpatrick, Edwin Hsing-Mean Sha:
Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications. DAC 2000: 540-545
Coauthor Index
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