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Marcello Lajolo
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2010 – 2019
- 2011
- [e1]Cristina Silvano
, Marcello Lajolo, Gianluca Palermo
Low Power Networks-on-Chip. Springer 2011, ISBN 978-1-4419-6910-1 [contents]
2000 – 2009
- 2008
- [c22]Simone Medardoni, Marcello Lajolo, Davide Bertozzi:
Variation tolerant NoC design by means of self-calibrating links. DATE 2008: 1402-1407 - 2007
- [j3]Gustavo de Veciana, Marcello Lajolo, Chen He, Enrico Macii, Sachin S. Sapatnekar:
In Memoriam: Margarida F. Jacome. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1549-1550 (2007) - [c21]André C. Nácul, Francesco Regazzoni
Hardware scheduling support in SMP architectures. DATE 2007: 642-647 - 2006
- [c20]Subhek Garg, Marcello Lajolo:
C-based Design of a Flexible Wrapper for Tiled Networks On Chip. FDL 2006: 185-189 - [c19]Sathish Chandra, Francesco Regazzoni, Marcello Lajolo:
Hardware/software partitioning of operating systems: a behavioral synthesis approach. ACM Great Lakes Symposium on VLSI 2006: 324-329 - 2005
- [c18]André C. Nácul, Marcello Lajolo, T. Givarjis:
Interface-Centric Abstraction Level for Rapid HW/SW Integration. FDL 2005: 329-341 - [c17]Francesco Regazzoni, André C. Nácul, Marcello Lajolo:
Automatic synthesis of the Hardware/Software Interface. FDL 2005: 401-405 - [c16]Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri:
SOFTENIT: a methodology for boosting the software content of system-on-chip designs. ACM Great Lakes Symposium on VLSI 2005: 361-366 - 2003
- [c15]Chen He, Marcello Lajolo, Margarida F. Jacome:
A Case Study of a System Level Approach to Exploration of Queuing Management Schemes for Input Queue Packet Switches. PDP 2003: 401-408 - 2002
- [j2]Marcello Lajolo, Anand Raghunathan
Cosimulation-based power estimation for system-on-chip design. IEEE Trans. Very Large Scale Integr. Syst. 10(3): 253-266 (2002) - [c14]Dirceu Cavendish, Marcello Lajolo, Hongbo Liu:
On the evaluation of fairness for input queue switches. ICC 2002: 996-1000 - [c13]Dirceu Cavendish, Marcello Lajolo, Hongbo Liu:
On the support of minimum service rates for input queue switches. ICC 2002: 1315-1320 - 2001
- [j1]Marcello Lajolo:
Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 974-982 (2001) - [c12]Marcello Lajolo, Matteo Sonza Reorda
Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. VLSI Design 2001: 371- - 2000
- [c11]Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante:
Automatic test bench generation for simulation-based validation. CODES 2000: 136-140 - [c10]Marcello Lajolo, Anand Raghunathan
Efficient Power Co-Estimation Techniques for System-on-Chip Design. DATE 2000: 27-34 - [c9]Marcello Lajolo, Maurizio Rebaudengo
Evaluating System Dependability in a Co-Design Framework. DATE 2000: 586-590 - [c8]Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda
System-level test bench generation in a co-design framework. ETW 2000: 25-30 - [c7]Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda
Behavioral-level test vector generation for system-on-chip designs. HLDVT 2000: 21-26 - [c6]Mihai T. Lazarescu
Compilation-based software performance estimation for system level design. HLDVT 2000: 167-172 - [c5]Marcello Lajolo, Luciano Lavagno, Matteo Sonza Reorda
Early Power Estimation for System-on-Chip Designs. PATMOS 2000: 108-117
1990 – 1999
- 1999
- [c4]Marcello Lajolo, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment. ASP-DAC 1999: 347- - [c3]Marcello Lajolo, Mihai T. Lazarescu, Alberto L. Sangiovanni-Vincentelli:
A compilation-based software estimation scheme for hardware/software co-simulation. CODES 1999: 85-89 - 1998
- [c2]Jie Liu, Marcello Lajolo, Alberto L. Sangiovanni-Vincentelli:
Software timing analysis using HW/SW cosimulation and instruction set simulator. CODES 1998: 65-69 - [c1]Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
A case study on modeling shared memory access effects during performance analysis of HW/SW systems. CODES 1998: 117-121
Coauthor Index
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