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Purushotham Murugappa
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2010 – 2019
- 2019
- [c10]Souradip Sarkar, Purushotham Murugappa, Manil Dev Gomony
:
A Reconfigurable Architecture for Posit Arithmetic. DSD 2019: 82-87 - 2016
- [j1]Vianney Lapotre
A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 383-387 (2016) - 2013
- [c9]Purushotham Murugappa, Amer Baghdadi, Michel Jézéquel:
Parameterized area-efficient multi-standard turbo decoder. DATE 2013: 109-114 - [c8]Vianney Lapotre
Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder. DSD 2013: 155-162 - [c7]Vianney Lapotre
Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder. ISCAS 2013: 493-496 - [c6]Vianney Lapotre, Purushotham Murugappa, Guy Gogniat
A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context. ISVLSI 2013: 40-45 - [c5]Vianney Lapotre
An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture. ReCoSoC 2013: 1-8 - [c4]Purushotham Murugappa, Vianney Lapotre, Amer Baghdadi
Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes. RSP 2013: 87-93 - 2012
- [c3]Purushotham Murugappa, Jean-Noel Bazin, Amer Baghdadi
FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding. RSP 2012: 143-148 - 2011
- [c2]Purushotham Murugappa, Rachid Al-Khayat, Amer Baghdadi, Michel Jézéquel:
A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. DATE 2011: 228-233 - [c1]Rachid Al-Khayat, Purushotham Murugappa, Amer Baghdadi
Area and throughput optimized ASIP for multi-standard turbo decoding. International Symposium on Rapid System Prototyping 2011: 79-84
Coauthor Index
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