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Robert Bogdan Staszewski
2020 – today
- 2024
- [j130]Pingda Guan
, Ruichang Ma, Haikun Jia
A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces. IEEE J. Solid State Circuits 59(10): 3123-3141 (2024) - [j129]Zhong Gao
Canceling Fundamental Fractional Spurs Due to Self-Interference in a Digital Phase-Locked Loop. IEEE J. Solid State Circuits 59(11): 3716-3729 (2024) - [j128]Kai Xu
RFIC Reuse Techniques to Enable Ultra-Low-Power IoT: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 71(3): 1663-1669 (2024) - [c119]Feifan Hong, Teerachot Siriburanon, Robert Bogdan Staszewski:
A Mixer-BBPD-Based Real-Time I/Q Calibration Loop for High-Speed Ring-Oscillators. ICTA 2024: 142-143 - [c118]Xiangjian Kong, Kai Xu, Robert Bogdan Staszewski, Mingchao Jian, Chunbing Guo:
A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement. VLSI Technology and Circuits 2024: 1-2 - [c117]Sayan Kumar, Patchara Sawakewang, Teerachot Siriburanon
A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j127]Zhong Gao
A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit. IEEE J. Solid State Circuits 58(6): 1552-1571 (2023) - [j126]Xi Chen
A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness. IEEE J. Solid State Circuits 58(7): 1945-1958 (2023) - [j125]Zhong Gao
A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion. IEEE J. Solid State Circuits 58(9): 2526-2542 (2023) - [j124]Viet Nguyen
Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra-Low-Voltage VCO-Based ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. 70(3): 1043-1056 (2023) - [j123]Hieu Minh Nguyen
An Edge-Combining Frequency-Multiplying Class-D Power Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 70(2): 471-475 (2023) - [j122]Enis Kobal
A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1331-1335 (2023) - [j121]Ali Esmailiyan, Elena Blokhina
An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 1861-1865 (2023) - [c116]Eduard Alarcón, Sergi Abadal, Fabio Sebastiano, Masoud Babaie, Edoardo Charbon, Peter Haring Bolívar, Maurizio Palesi, Elena Blokhina, Dirk Leipold, Robert Bogdan Staszewski, Artur García-Sáez, Carmen G. Almudéver:
Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package. ISCAS 2023: 1-5 - [c115]Llorenç Fanals, Eduard Alarcón, Imran Bashir, Elena Blokhina, Dirk Leipold, Robert Bogdan Staszewski:
Tunable $LC$ resonator for multiplexed multi-qubit readout. ISCAS 2023: 1-5 - [c114]Weichen Tao, Weichen Zhao, Robert Bogdan Staszewski, Fujiang Lin, Yizhe Hu:
An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM. VLSI Technology and Circuits 2023: 1-2 - [c113]Kai Xu, Bowen Yu
A 50μW Ring-Type Complementary Inverse-Class-D Oscillator with 191.4dBc/Hz FoM and 205.6dBc/Hz FoMA. VLSI Technology and Circuits 2023: 1-2 - [i2]Eduard Alarcón, Sergi Abadal, Fabio Sebastiano, Masoud Babaie, Edoardo Charbon, Peter Haring Bolívar, Maurizio Palesi, Elena Blokhina, Dirk Leipold, Robert Bogdan Staszewski, Artur García-Sáez, Carmen G. Almudéver:
Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package. CoRR abs/2303.14008 (2023) - 2022
- [j120]Amir Bozorg
A Clock-Phase Reuse Technique for Discrete-Time Bandpass Filters. IEEE J. Solid State Circuits 57(1): 290-301 (2022) - [j119]Jianglin Du
A Compact 0.2-0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise Over Wide Tuning Range. IEEE J. Solid State Circuits 57(2): 452-464 (2022) - [j118]Yizhe Hu
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking. IEEE J. Solid State Circuits 57(2): 518-534 (2022) - [j117]Hieu Minh Nguyen
A mm-Wave Switched-Capacitor RFDAC. IEEE J. Solid State Circuits 57(4): 1224-1238 (2022) - [j116]Viet Nguyen
A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC. IEEE J. Solid State Circuits 57(6): 1684-1699 (2022) - [j115]Yue Chen
A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and pp Supply Ripple. IEEE J. Solid State Circuits 57(6): 1749-1764 (2022) - [j114]Amir Bozorg
A Charge-Sharing IIR Filter With Linear Interpolation and High Stopband Rejection. IEEE J. Solid State Circuits 57(7): 2090-2101 (2022) - [j113]Gholamreza Nikandish
A Broadband Fully Integrated Power Amplifier Using Waveform Shaping Multi-Resonance Harmonic Matching Network. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 2-15 (2022) - [j112]Amir Bozorg
A 20 MHz-2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 42-50 (2022) - [j111]Peng Chen
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 51-63 (2022) - [j110]Peng Chen
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69(1): 196-206 (2022) - [j109]Xi Chen
Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 973-984 (2022) - [j108]Enis Kobal
A Gm-Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 5007-5017 (2022) - [j107]Yizhe Hu
Multirate Timestamp Modeling for Ultralow-Jitter Frequency Synthesis: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3030-3036 (2022) - [j106]Sandro Binsfeld Ferreira
Design of High-IF Discrete-Time Receivers for IoT: Demystifying Aliasing Trade-Offs. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3078-3083 (2022) - [c112]Dennis Andrade-Miceli, Conor Power, Ali Esmailiyan, Teerachot Siriburanon
Characterisation and Modelling of 22-nm FD-SOI Transistors Operating at Cryogenic Temperatures. ICECS 2022 2022: 1-4 - [c111]Conor Power, Dennis Andrade-Miceli, Imran Bashir, Mike Asker, Dirk Leipold, Robert Bogdan Staszewski, Elena Blokhina:
Modelling of Electron Injection and Confinement in Cryogenic 22-nm FD-SOI Quantum Dot Arrays. ICECS 2022 2022: 1-4 - [c110]Conor Power, Robert Bogdan Staszewski, Elena Blokhina:
Cryogenic Transistor Confinement Well Simulation through Material and Carrier Transport Decoupling. ICECS 2022 2022: 1-2 - [c109]Xutong Wu, Panagiotis Giounanlis, Robert Bogdan Staszewski, Elena Blokhina:
Control of Quantum Systems: Comparison of Different Techniques by the Example of Charge and Spin Semiconductor Qubits. ICECS 2022 2022: 1-4 - [c108]Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski:
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur. ISSCC 2022: 1-3 - [c107]Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi
A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs. ISSCC 2022: 380-382 - [c106]Zhong Gao, Martin Fritz, Jingchu He, Gerd Spalink, Robert Bogdan Staszewski, Morteza S. Alavi
A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation. VLSI Technology and Circuits 2022: 14-15 - 2021
- [j105]Gholamreza Nikandish
Unbalanced Power Amplifier: An Architecture for Broadband Back-Off Efficiency Enhancement. IEEE J. Solid State Circuits 56(2): 367-381 (2021) - [j104]Amir Bozorg
A 0.02-4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse. IEEE J. Solid State Circuits 56(2): 404-415 (2021) - [j103]Suoping Hu
A Type-II Phase-Tracking Receiver. IEEE J. Solid State Circuits 56(2): 427-439 (2021) - [j102]Mohamed Atef Shehata
A Distributed Stubs Technique to Mitigate Flicker Noise Upconversion in a mm-Wave Rotary Traveling-Wave Oscillator. IEEE J. Solid State Circuits 56(6): 1745-1760 (2021) - [j101]Jianglin Du
A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL. IEEE J. Solid State Circuits 56(11): 3445-3457 (2021) - [j100]Ali Esmailiyan
Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS. IEEE Open J. Circuits Syst. 2: 23-31 (2021) - [j99]Mojtaba Bagheri
Interchannel Mismatch Calibration Techniques for Time-Interleaved SAR ADCs. IEEE Open J. Circuits Syst. 2: 420-433 (2021) - [j98]Elena Blokhina
Towards the Co-Simulation of Charge Qubits: A Methodology Grounding on an Equivalent Circuit Representation. IEEE Open J. Circuits Syst. 2: 548-563 (2021) - [j97]Feifei Zhang
An Active-Under-Coil RFDAC With Analog Linear Interpolation in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 1855-1868 (2021) - [j96]Chao-Chieh Li
A Compact Transformer-Based Fractional-N ADPLL in 10-nm FinFET CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(5): 1881-1891 (2021) - [j95]Suoping Hu
A 0.7-V Sub-mW Type-II Phase-Tracking Bluetooth Low Energy Receiver in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(6): 2317-2328 (2021) - [j94]Gholamreza Nikandish
A Fully Integrated GaN Dual-Channel Power Amplifier With Crosstalk Suppression for 5G Massive MIMO Transmitters. IEEE Trans. Circuits Syst. II Express Briefs 68(1): 246-250 (2021) - [j93]Yizhe Hu
Oscillator Flicker Phase Noise: A Tutorial. IEEE Trans. Circuits Syst. II Express Briefs 68(2): 538-544 (2021) - [j92]Hanie Ghaedrahmati
A 38.6-fJ/Conv.-Step Inverter-Based Continuous-Time Bandpass ΔΣ ADC in 28 nm Using Asynchronous SAR Quantizer. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3113-3117 (2021) - [c105]Imran Bashir, Dirk Leipold, Mike Asker, Ali Esmailiyan, Elena Blokhina, David Redmond, Panagiotis Giounanlis, Dennis Andrade-Miceli, Robert Bogdan Staszewski:
Bias Generation and Calibration of CMOS Charge Qubits at 3.5 Kelvin in 22-nm FDSOI. ESSCIRC 2021: 47-50 - [c104]Amir Bozorg
A Charge-Rotating IIR Filter with Linear Interpolation and High Stop-Band Rejection. ESSCIRC 2021: 335-338 - [c103]Enis Kobal
A 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOS. ESSCIRC 2021: 377-380 - [c102]Imran Bashir, Dirk Leipold, Mike Asker, Ali Esmailiyan, Elena Blokhina, David Redmond, Panagiotis Giounanlis, Dennis Andrade-Miceli, Robert Bogdan Staszewski:
Bias Generation and Calibration of CMOS Charge Qubits at 3.5 Kelvin in 22-nm FDSOI. ESSDERC 2021: 47-50 - [c101]Ramesh Harjani, Mike Chen, Marco Berkhout, Johan H. C. van den Heuvel, Thomas H. Lee, Robert Bogdan Staszewski, Kathleen Philips, Howard C. Luong, Vadim Ivanov:
SE3: Favorite Circuit Design and Testing Mistakes of Starting Engineers. ISSCC 2021: 541-542 - [c100]Peng Chen, Feifei Zhang
A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range. VLSI Circuits 2021: 1-2 - [c99]Jianglin Du
A 24-31 GHz Reference Oversampling ADPLL Achieving FoMjitter-N of -269.3 dB. VLSI Circuits 2021: 1-2 - [c98]Hieu Minh Nguyen, Jeffrey S. Walling
A Ka-band Switched-Capacitor RFDAC Using Edge-Combining in 22nm FD-SOI. VLSI Circuits 2021: 1-2 - [i1]Imran Bashir, Dirk Leipold, Elena Blokhina, Mike Asker, David Redmond, Ali Esmailiyan, Panagiotis Giounanlis, Hans Haenlein, Xuton Wu, Andrii Sokolov, Dennis Andrade-Miceli, Robert Bogdan Staszewski:
Monolithic Integration of Quantum Resonant Tunneling Gate on a 22nm FD-SOI CMOS Process. CoRR abs/2112.04586 (2021) - 2020
- [j91]Elena Blokhina
CMOS Position-Based Charge Qubits: Theoretical Analysis of Control and Entanglement. IEEE Access 8: 4182-4197 (2020) - [j90]Hongying Wang
An Event-Driven Quasi-Level-Crossing Delta Modulator Based on Residue Quantization. IEEE J. Solid State Circuits 55(2): 298-311 (2020) - [j89]Kai Xu
A Single-Pin Antenna Interface RF Front End Using a Single-MOS DCO-PA and a Push-Pull LNA. IEEE J. Solid State Circuits 55(8): 2055-2068 (2020) - [j88]Ka-Fai Un
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection. IEEE Trans. Circuits Syst. II Express Briefs 67-II(1): 37-41 (2020) - [j87]Hongying Wang
Passive SC ΔΣ Modulator Based on Pipelined Charge-Sharing Rotation in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(2): 578-589 (2020) - [j86]Ali Esmailiyan
A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump-Based Comparators in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(6): 1789-1802 (2020) - [j85]Ying Wu
A Time-Domain 147fsrms 2.5-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(8): 2532-2545 (2020) - [j84]Mojtaba Bagheri
A Mismatch Calibration Technique for SAR ADCs Based on Deterministic Self-Calibration and Stochastic Quantization. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(9): 2883-2896 (2020) - [j83]Alessandro Urso
A Switched-Capacitor DC-DC Converter Powering an LC Oscillator to Achieve 85% System Peak Power Efficiency and -65dBc Spurious Tones. IEEE Trans. Circuits Syst. 67-I(11): 3764-3777 (2020) - [j82]Hongying Wang
An Adaptive-Resolution Quasi-Level-Crossing Delta Modulator With VCO-Based Residue Quantizer. IEEE Trans. Circuits Syst. 67-II(12): 2828-2832 (2020) - [j81]Chao-Chieh Li
A 0.2-V Three-Winding Transformer-Based DCO in 16-nm FinFET CMOS. IEEE Trans. Circuits Syst. 67-II(12): 2878-2882 (2020) - [j80]Gholamreza Nikandish
Broadband Fully Integrated GaN Power Amplifier With Minimum-Inductance BPF Matching and Two-Transistor AM-PM Compensation. IEEE Trans. Circuits Syst. 67-I(12): 4211-4223 (2020) - [c97]Andrii Sokolov
Simulation Methodology for Electron Transfer in CMOS Quantum Dots. ICCS (6) 2020: 650-663 - [c96]Panagiotis Giounanlis, Andrii Sokolov
Electrostatic Control and Entanglement of CMOS Position-Based Qubits. ISCAS 2020: 1-5 - [c95]Robert Bogdan Staszewski, Panagiotis Giounanlis, Ali Esmailiyan, Hongying Wang, Imran Bashir, Cagri Cetintepe, Dennis Andrade-Miceli, Mike Asker, Dirk Leipold, Teerachot Siriburanon, Andrii Sokolov
Position-Based CMOS Charge Qubits for Scalable Quantum Processors at 4K. ISCAS 2020: 1-5 - [c94]Yizhe Hu, Xi Chen
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM. ISSCC 2020: 276-278 - [c93]Minyoung Song
30.8 A 3.5mm×3.8mm Crystal-Less MICS Transceiver Featuring Coverages of ±160ppm Carrier Frequency Offset and 4.8-VSWR Antenna Impedance for Insertable Smart Pills. ISSCC 2020: 474-476
2010 – 2019
- 2019
- [j79]Mahsa Keshavarz Hedayati
Challenges in On-Chip Antenna Design and Integration With RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems. IEEE Access 7: 43190-43204 (2019) - [j78]Panagiotis Giounanlis
Modeling of Semiconductor Electrostatic Qubits Realized Through Coupled Quantum Dots. IEEE Access 7: 49262-49278 (2019) - [j77]Gholamreza Nikandish
Design of Highly Linear Broadband Continuous Mode GaN MMIC Power Amplifiers for 5G. IEEE Access 7: 57138-57150 (2019) - [j76]Gholamreza Nikandish
Bandwidth Enhancement of GaN MMIC Doherty Power Amplifiers Using Broadband Transformer-Based Load Modulation Network. IEEE Access 7: 119844-119855 (2019) - [j75]Yue Chen
A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation. IEEE J. Solid State Circuits 54(1): 240-252 (2019) - [j74]Zhirui Zong
A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications. IEEE J. Solid State Circuits 54(3): 755-767 (2019) - [j73]Yao-Hong Liu
Design and Analysis of a DCO-Based Phase-Tracking RF Receiver for IoT Applications. IEEE J. Solid State Circuits 54(3): 785-795 (2019) - [j72]Umanath Kamath
A 1-V Bandgap Reference in 7-nm FinFET With a Programmable Temperature Coefficient and Inaccuracy of ±0.2% From -45°C to 125°C. IEEE J. Solid State Circuits 54(7): 1830-1840 (2019) - [j71]Kai Xu
A 0.85mm2 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD2 Self-Suppression and Pulling Mitigation. IEEE J. Solid State Circuits 54(7): 2028-2037 (2019) - [j70]Peng Chen
A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS. IEEE J. Solid State Circuits 54(11): 3075-3085 (2019) - [j69]Yizhe Hu
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 1962-1966 (2019) - [c92]Vivek Govindaraj, Jianglin Du
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization. APCCAS 2019: 81-84 - [c91]Jianglin Du
A 0.3V, 35% Tuning-Range, 60kHz 1/f3-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS. CICC 2019: 1-4 - [c90]Jakub Szyduczynski
Behavioral Modelling and Optimization of a Cyclic Feedback-Based Successive Approximation TDC with Dynamic Delay Equalization. EBCCSP 2019: 1-9 - [c89]Feng-Wei Kuo, Zhirui Zong
A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic. ESSCIRC 2019: 53-56 - [c88]Mohamed Atef Shehata
A 184.6-dBc/Hz FoM 100-kHz Flicker Phase Noise Corner 30-GHz Rotary Traveling-Wave Oscillator Using Distributed Stubs in 22-nm FD-SOI. ESSCIRC 2019: 103-106 - [c87]Imran Bashir
A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip. ESSCIRC 2019: 125-128 - [c86]Gholamreza Nikandish, Robert Bogdan Staszewski
Broadband Fully Integrated GaN Power Amplifier With Embedded Minimum Inductor Bandpass Filter and AM-PM Compensation. ESSCIRC 2019: 159-162 - [c85]Panagiotis Giounanlis, Elena Blokhina
A Python-Verilog Toolbox for Modeling of a Hadamard Gate Based on Position-Based CMOS Qubits. ICECS 2019: 566-569 - [c84]Imran Bashir
A Verilog-A Model of the Shuttle of an Electron in a Two Quantum-Dot System. NEWCAS 2019: 1-4 - [c83]Amir Bozorg
Two-Fold Noise-Cancelling Low-Noise Amplifier in 28-nm CMOS. NEWCAS 2019: 1-4 - [c82]Zhong Gao
28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications. NEWCAS 2019: 1-4 - 2018
- [j68]Bishnu Patra
Cryo-CMOS Circuits and Systems for Quantum Computing Applications. IEEE J. Solid State Circuits 53(1): 309-321 (2018) - [j67]Yizhe Hu
A Low-Flicker-Noise 30-GHz Class-F23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path. IEEE J. Solid State Circuits 53(7): 1977-1987 (2018) - [j66]Naser Pourmousavian
A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS. IEEE J. Solid State Circuits 53(9): 2572-2583 (2018) - [j65]Chao-Chieh Li, Min-Shueh Yuan
All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply. IEEE J. Solid State Circuits 53(12): 3660-3671 (2018) - [j64]Mahsa Keshavarz Hedayati
A 33-GHz LNA for 5G Wireless Systems in 28-nm Bulk CMOS. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1460-1464 (2018) - [j63]Peng Chen
An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3734-3744 (2018) - [j62]Feng-Wei Kuo
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3756-3768 (2018) - [c81]Kai Xu, Jun Yin
A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA. A-SSCC 2018: 293-294 - [c80]Umanath Kamath, Edward Cullen, John Jennings, Ionut Cical, Darragh Walsh, Peng Lim, Brendan Farley, Robert Bogdan Staszewski
A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from -45°C to 125°C. ESSCIRC 2018: 78-81 - [c79]Umanath Kamath, Tao Yu, Wei Yao, Edward Cullen, John Jennings, Susan Wu, Peng Lim, Brendan Farley, Robert Bogdan Staszewski
BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-nm FinFET. ESSDERC 2018: 86-89 - [c78]Panagiotis Giounanlis
Occupancy Oscillations and Electron Transfer in Multiple-Quantum-Dot Qubits and their Circuit Representation. ICECS 2018: 153-156 - [c77]Min-Shueh Yuan, Chao-Chieh Li, Chia-Chun Liao, Yu-Tso Lin, Chih-Hsien Chang, Robert Bogdan Staszewski
A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference. ISSCC 2018: 448-450 - [c76]Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski
A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW. VLSI Circuits 2018: 183-184 - 2017
- [j61]Feng-Wei Kuo
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network. IEEE J. Solid State Circuits 52(4): 1144-1162 (2017) - [j60]Eugenio Cantatore
Introduction to the Special Issue on the 46th European Solid-State Circuits Conference (ESSCIRC). IEEE J. Solid State Circuits 52(7): 1700-1702 (2017) - [j59]Ying Wu
A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase Noise. IEEE J. Solid State Circuits 52(7): 1885-1903 (2017) - [j58]Mina Shahmohammadi
Tuning Range Extension of a Transformer-Based Oscillator Through Common-Mode Colpitts Resonance. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(4): 836-846 (2017) - [j57]Yao-Hong Liu
An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(5): 1094-1105 (2017) - [j56]Massoud Tohidian
A Fully Integrated Discrete-Time Superheterodyne Receiver. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 635-647 (2017) - [c75]Peng Chen
A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS. A-SSCC 2017: 93-96 - [c74]Yue Chen
A 350-mV 2.4-GHz quadrature oscillator with nearly instantaneous start-up using series LC tanks. A-SSCC 2017: 104-108 - [c73]Viet Nguyen, Filippo Schembari, Robert Bogdan Staszewski
Oscillator-based ADCs: An exploration of time-mode analog-to-digital conversion. EBCCSP 2017: 1-6 - [c72]Hongying Wang, Filippo Schembari, Robert Bogdan Staszewski
Frequency-domain adaptive-resolution level-crossing-sampling ADC. EBCCSP 2017: 1-5 - [c71]Yizhe Hu
A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f3 corner. ESSCIRC 2017: 87-90 - [c70]Edoardo Charbon, Fabio Sebastiano
15.5 Cryo-CMOS circuits and systems for scalable quantum computing. ISSCC 2017: 264-265 - [c69]Chao-Chieh Li, Min-Shueh Yuan, Chih-Hsien Chang, Yu-Tso Lin, Chia-Chun Liao, Kenny Hsieh, Mark Chen, Robert Bogdan Staszewski
19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications. ISSCC 2017: 332-333 - [c68]Yao-Hong Liu
24.1 A 770pJ/b 0.85V 0.3mm2 DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applications. ISSCC 2017: 408-409 - 2016
- [j55]Imran Bashir
A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation. J. Electron. Test. 32(4): 437-445 (2016) - [j54]Iman Madadi
A High IIP2 SAW-Less Superheterodyne Receiver With Multistage Harmonic Rejection. IEEE J. Solid State Circuits 51(2): 332-347 (2016) - [j53]Zhirui Zong
A 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit Multiplier. IEEE J. Solid State Circuits 51(5): 1261-1273 (2016) - [j52]Imran Bashir
A Digitally Controlled Injection-Locked Oscillator With Fine Frequency Resolution. IEEE J. Solid State Circuits 51(6): 1347-1360 (2016) - [j51]Masoud Babaie, Feng-Wei Kuo, Huan-Neng Ron Chen, Lan-Chou Cho, Chewnpu Jou, Fu-Lung Hsueh, Mina Shahmohammadi, Robert Bogdan Staszewski
A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm. IEEE J. Solid State Circuits 51(7): 1547-1565 (2016) - [j50]Mina Shahmohammadi
A 1/f Noise Upconversion Reduction Technique for Voltage-Biased RF CMOS Oscillators. IEEE J. Solid State Circuits 51(11): 2610-2624 (2016) - [j49]Seyed Amir Reza Ahmadi Mehr
Analysis and Design of a Multi-Core Oscillator for Ultra-Low Phase Noise. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(4): 529-539 (2016) - [j48]Seyed Amir Reza Ahmadi Mehr
Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division. IEEE Trans. Very Large Scale Integr. Syst. 24(3): 1071-1082 (2016) - [c67]Ying Wu, Robert Bogdan Staszewski
A 0.5ps 1.4mW 50MS/s Nyquist bandwidth time amplifier based two-step flash-ΔΣ time-to-digital converter. EBCCSP 2016: 1-4 - [c66]Peng Chen
Exponential extended flash time-to-digital converter. EBCCSP 2016: 1-4 - [c65]Ying Wu, Mina Shahmohammadi, Yue Chen
A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise. ESSCIRC 2016: 209-212 - [c64]Feng-Wei Kuo, Sandro Binsfeld Ferreira
A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter. VLSI Circuits 2016: 1-2 - [c63]Chao-Chieh Li, Tsung-Hsien Tsai, Min-Shueh Yuan, Chia-Chun Liao, Chih-Hsien Chang, Tien-Chien Huang, Hsien-Yuan Liao, Chung-Ting Lu, Hung-Yi Kuo, Kenny Hsieh, Mark Chen, Augusto Ronchini Ximenes, Robert Bogdan Staszewski
A 0.034mm2, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j47]Masoud Babaie, Robert Bogdan Staszewski
An Ultra-Low Phase Noise Class-F 2 CMOS Oscillator With 191 dBc/Hz FoM and Long-Term Reliability. IEEE J. Solid State Circuits 50(3): 679-692 (2015) - [j46]Jingcheng Zhuang, Khurram Waheed, Robert Bogdan Staszewski
Design of Spur-Free ΣΔ Frequency Tuning Interface for Digitally Controlled Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 62-II(1): 46-50 (2015) - [j45]Iman Madadi
Analysis and Design of I/Q Charge-Sharing Band-Pass-Filter for Superheterodyne Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(8): 2114-2121 (2015) - [c62]Peng Chen
Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs. ESSCIRC 2015: 283-286 - [c61]Feng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Kyle Yen, Jinn-Yeh Chien, Lanchou Cho, Fred Kuo, Chewnpu Jou, Fu-Lung Hsueh, Robert Bogdan Staszewski
A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm. ESSCIRC 2015: 356-359 - [c60]Bindi Wang, Yao-Hong Liu
A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS. ISCAS 2015: 2289-2292 - [c59]Peng Chen
Fractional spur suppression in all-digital phase-locked loops. ISCAS 2015: 2565-2568 - [c58]Mina Shahmohammadi, Masoud Babaie, Robert Bogdan Staszewski
25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators. ISSCC 2015: 1-3 - [c57]Tsung-Hsien Tsai, Min-Shueh Yuan, Chih-Hsien Chang, Chia-Chun Liao, Chao-Chieh Li, Robert Bogdan Staszewski
14.5 A 1.22ps integrated-jitter 0.25-to-4GHz fractional-N ADPLL in 16nm FinFET CM0S. ISSCC 2015: 1-3 - [c56]Iman Madadi
A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS. VLSIC 2015: 308- - 2014
- [j44]Jingcheng Zhuang, Robert Bogdan Staszewski:
All-Digital RF Phase-Locked Loops Exploiting Phase Prediction. Inf. Media Technol. 9(1): 1-14 (2014) - [j43]Jingcheng Zhuang, Robert Bogdan Staszewski
All-Digital RF Phase-Locked Loops Exploiting Phase Prediction. IPSJ Trans. Syst. LSI Des. Methodol. 7: 2-15 (2014) - [j42]Akshay Visweswaran, Robert Bogdan Staszewski
A Low Phase Noise Oscillator Principled on Transformer-Coupled Hard Limiting. IEEE J. Solid State Circuits 49(2): 373-383 (2014) - [j41]Wanghua Wu, Robert Bogdan Staszewski
A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS. IEEE J. Solid State Circuits 49(5): 1081-1096 (2014) - [j40]Massoud Tohidian
Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter. IEEE J. Solid State Circuits 49(11): 2575-2587 (2014) - [c55]Akshay Visweswaran, John R. Long, Robert Bogdan Staszewski
A 1.2V 110-MHz-UGB differential class-AB amplifier in 65nm CMOS. CICC 2014: 1-4 - [c54]Wanghua Wu, Robert Bogdan Staszewski
Design for test of a mm-Wave ADPLL-based transmitter. CICC 2014: 1-8 - [c53]Massoud Tohidian
3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver. ISSCC 2014: 1-3 - [c52]Vamshi Krishna Chillara, Yao-Hong Liu
9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications. ISSCC 2014: 172-173 - [c51]Feng-Wei Kuo, Huan-Neng Ron Chen, Kyle Yen, Hsien-Yuan Liao, Chewnpu Jou, Fu-Lung Hsueh, Masoud Babaie, Robert Bogdan Staszewski
A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS. VLSIC 2014: 1-2 - 2013
- [j39]Wanghua Wu, John R. Long, Robert Bogdan Staszewski
High-Resolution Millimeter-Wave Digitally Controlled Oscillators With Reconfigurable Passive Resonators. IEEE J. Solid State Circuits 48(11): 2785-2794 (2013) - [j38]Masoud Babaie, Robert Bogdan Staszewski
A Class-F CMOS Oscillator. IEEE J. Solid State Circuits 48(12): 3120-3133 (2013) - [c50]Masoud Babaie, Robert Bogdan Staszewski
A study of RF oscillator reliability in nanoscale CMOS. ECCTD 2013: 1-4 - [c49]Jingcheng Zhuang, Robert Bogdan Staszewski
Gain Estimation of a Digital-to-Time Converter for Phase-Prediction All-Digital PLL. ECCTD 2013: 1-4 - [c48]Seyed Amir Reza Ahmadi Mehr
Frequency translation through fractional division for a two-channel pulling mitigation. ESSCIRC 2013: 241-244 - [c47]Massoud Tohidian
A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOS. ISSCC 2013: 174-175 - [c46]Jie-Wei Lai, Chi-Hsueh Wang, Kaipon Kao, Anson Lin, Yi-Hsien Cho, Lan-chou Cho, Meng-Hsiung Hung, Xin-Yu Shih
A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS. ISSCC 2013: 342-343 - [c45]Masoud Babaie, Robert Bogdan Staszewski
Third-harmonic injection technique applied to a 5.87-to-7.56GHz 65nm CMOS Class-F oscillator with 192dBc/Hz FOM. ISSCC 2013: 348-349 - [c44]Wanghua Wu, Xuefei Bai, Robert Bogdan Staszewski
A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS. ISSCC 2013: 352-353 - 2012
- [j37]Robert Bogdan Staszewski
Digitally intensive wireless transceivers. IEEE Des. Test 29(6): 7-18 (2012) - [c43]Wenlong Jiang, Armin Tavakol, Popong Effendrik, Marcel van de Gevel, Frank Verwaal, Robert Bogdan Staszewski
Design of ADPLL system for WiMAX applications in 40-nm CMOS. ICECS 2012: 73-76 - [c42]Jingcheng Zhuang, Robert Bogdan Staszewski
A low-power all-digital PLL architecture based on phase prediction. ICECS 2012: 797-800 - [c41]Priyanka Kumar, Edoardo Charbon, Robert Bogdan Staszewski
Low power time-of-flight 3D imager system in standard CMOS. ICECS 2012: 941-944 - [c40]Robert Bogdan Staszewski
Session 20 overview: RF frequency generation: RF subcommittee. ISSCC 2012: 340-341 - [c39]Akshay Visweswaran, Robert Bogdan Staszewski
A clip-and-restore technique for phase desensitization in a 1.2V 65nm CMOS oscillator for cellular mobile and base stations. ISSCC 2012: 350-352 - [c38]Robert Bogdan Staszewski
Is RF doomed to digitization? What shall RF circuit designers do? ISSCC 2012: 510 - 2011
- [j36]Oren E. Eliezer, Robert Bogdan Staszewski
Built-In Measurements in Low-Cost Digital-RF Transceivers. IEICE Trans. Electron. 94-C(6): 930-937 (2011) - [j35]Imran Bashir
A Novel Approach for Mitigation of RF Oscillator Pulling in a Polar Transmitter. IEEE J. Solid State Circuits 46(2): 403-415 (2011) - [j34]Robert Bogdan Staszewski
Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS. IEEE J. Solid State Circuits 46(12): 2904-2919 (2011) - [j33]Robert Bogdan Staszewski
State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(7): 1497-1510 (2011) - [j32]Khurram Waheed, Robert Bogdan Staszewski
Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2051-2060 (2011) - [j31]Min C. Park, Michael H. Perrott, Robert Bogdan Staszewski
An Amplitude Resolution Improvement of an RF-DAC Employing Pulsewidth Modulation. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(11): 2590-2603 (2011) - [c37]Morteza S. Alavi
A 2-GHz digital I/Q modulator in 65-nm CMOS. A-SSCC 2011: 277-280 - [c36]Popong Effendrik, Wenlong Jiang, Marcel van de Gevel, Frank Verwaal, Robert Bogdan Staszewski
Time-to-digital converter (TDC) for WiMAX ADPLL in 40-nm CMOS. ECCTD 2011: 365-368 - [c35]Robert Bogdan Staszewski
Digital RF architectures for wireless transceivers (invited). ECCTD 2011: 429-436 - [c34]Imran Bashir, Robert Bogdan Staszewski
Autonomous predistortion calibration of an RF power amplifier. ISCAS 2011: 205-208 - [c33]Robert Bogdan Staszewski
All-digital RF frequency modulation. ISCAS 2011: 426-429 - [c32]Robert Bogdan Staszewski
Spur-free all-digital PLL in 65nm for mobile phones. ISSCC 2011: 52-54 - [c31]Gabriele Manganaro, Domine Leenaerts, Francesco Dantoni, Andrea Baschirotto, Robert Bogdan Staszewski
Advanced transmitters for wireless infrastructure. ISSCC 2011: 512-513 - [c30]John R. Long, Hooman Darabi, Frank Op't Eynde, Behzad Razavi, Robert Bogdan Staszewski
Cellular and wireless LAN transceivers: From systems to circuit design. ISSCC 2011: 524 - 2010
- [j30]Roman Staszewski, Robert Bogdan Staszewski
Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS. IEEE J. Solid State Circuits 45(2): 276-288 (2010) - [j29]Jaimin Mehta, Vasile Zoicas, Oren E. Eliezer, Robert Bogdan Staszewski
An Efficient Linearization Scheme for a Digital Polar EDGE Transmitter. IEEE Trans. Circuits Syst. II Express Briefs 57-II(3): 193-197 (2010) - [j28]Min C. Park, Michael H. Perrott, Robert Bogdan Staszewski
A Time-Domain Resolution Improvement of an RF-DAC. IEEE Trans. Circuits Syst. II Express Briefs 57-II(7): 517-521 (2010) - [j27]Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski
Recombination of Envelope and Phase Paths in Wideband Polar Transmitters. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8): 1891-1904 (2010) - [j26]Jingcheng Zhuang, Khurram Waheed, Robert Bogdan Staszewski
A Technique to Reduce Phase/Frequency Modulation Bandwidth in a Polar RF Transmitter. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(8): 2196-2207 (2010) - [c29]Khurram Waheed, Mahbuba Sheba, Robert Bogdan Staszewski
Spurious free time-to-digital conversion in an ADPLL using short dithering sequences. CICC 2010: 1-4 - [c28]Robert Bogdan Staszewski
State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS. ISCAS 2010: 229-232 - [c27]Jaimin Mehta, Robert Bogdan Staszewski
A 0.8mm2 all-digital SAW-less polar transmitter in 65nm EDGE SoC. ISSCC 2010: 58-59 - [c26]Robert Bogdan Staszewski
Can RF SoCs (Self)test their own RF? ISSCC 2010: 530-531
2000 – 2009
- 2009
- [j25]Oren Eytan Eliezer, Robert Bogdan Staszewski
A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers. IEEE J. Solid State Circuits 44(5): 1436-1453 (2009) - [c25]Jawaharlal Tangudu, Sarma Gunturi, Saket Jalan, Jayawardan Janardhanan, Raghu Ganesan, Debapriya Sahu, Khurram Waheed, John L. Wallberg, Robert Bogdan Staszewski
Quantization Noise Improvement of Time to Digital Converter (TDC) for ADPLL. ISCAS 2009: 1020-1023 - 2008
- [j24]Ioannis L. Syllaios, Robert Bogdan Staszewski
Time-Domain Modeling of an RF All-Digital PLL. IEEE Trans. Circuits Syst. II Express Briefs 55-II(6): 601-605 (2008) - [c24]Khurram Waheed, Robert Bogdan Staszewski
Mitigation of CMOS device variability in the transmitter amplitude path using Digital RF Processing. ISCAS 2008: 568-571 - [c23]Khurram Waheed, Robert Bogdan Staszewski
Curse of digital polar transmission: Precise delay alignment in amplitude and phase modulation paths. ISCAS 2008: 3142-3145 - [c22]Robert Bogdan Staszewski
A 24mm2 Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS. ISSCC 2008: 208-209 - 2007
- [j23]Khurram Muhammad, Thomas Murphy, Robert Bogdan Staszewski
Verification of Digital RF Processors: RF, Analog, Baseband, and Software. IEEE J. Solid State Circuits 42(5): 992-1002 (2007) - [j22]Robert Bogdan Staszewski
All-Digital PLL With Ultra Fast Settling. IEEE Trans. Circuits Syst. II Express Briefs 54-II(2): 181-185 (2007) - [j21]Robert Bogdan Staszewski
RF Built-in Self Test of a Wireless Transmitter. IEEE Trans. Circuits Syst. II Express Briefs 54-II(2): 186-190 (2007) - [c21]Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski
Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications. CICC 2007: 861-864 - [c20]Khurram Waheed, Robert Bogdan Staszewski
Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS. ISCAS 2007: 1253-1256 - [c19]Khurram Waheed, Robert Bogdan Staszewski
Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation. ISCAS 2007: 3291-3294 - [c18]Ian Galton, Matt Miller, Robert Bogdan Staszewski
Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS. ISSCC 2007: 635-636 - [c17]Ioannis L. Syllaios, Poras T. Balsara, Robert Bogdan Staszewski
On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios. PIMRC 2007: 1-6 - 2006
- [j20]Yo-Chuol Ho, Robert Bogdan Staszewski
Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers. EURASIP J. Wirel. Commun. Netw. 2006 (2006) - [j19]Krzysztof Iniewski, Mourad N. El-Gamal, Robert Bogdan Staszewski
CMOS RF Circuits for Wireless Applications. EURASIP J. Wirel. Commun. Netw. 2006 (2006) - [j18]Jinseok Koh, Gabriel Gomez, Khurram Muhammad, Robert Bogdan Staszewski
A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS. EURASIP J. Wirel. Commun. Netw. 2006 (2006) - [j17]Chih-Ming Hung
A digitally controlled oscillator system for SAW-less transmitters in cellular handsets. IEEE J. Solid State Circuits 41(5): 1160-1170 (2006) - [j16]Khurram Muhammad, Yo-Chuol Ho, Terry Mayhugh Jr., Chih-Ming Hung
The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process. IEEE J. Solid State Circuits 41(8): 1772-1783 (2006) - [j15]Robert Bogdan Staszewski
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 53-II(3): 220-224 (2006) - [j14]Robert Bogdan Staszewski
LMS-based calibration of an RF digitally controlled oscillator for mobile phones. IEEE Trans. Circuits Syst. II Express Briefs 53-II(3): 225-229 (2006) - [c16]Robert Bogdan Staszewski
Software Assisted Digital RF Processor for Single-Chip GSM Radio in 90 nm CMOS. CICC 2006: 81-84 - [c15]Siray Akhtar, Mehmet Ipek, J. Lin, Robert Bogdan Staszewski
Quad Band Digitally Controlled Oscillator for WCDMA Transmitter in 90nm CMOS. CICC 2006: 129-132 - [c14]Robert Bogdan Staszewski
Digital Signal Processing for RF at 45-nm CMOS and Beyond. CICC 2006: 517-522 - [c13]Robert Bogdan Staszewski
Digital RF Processor Techniques for Single-Chip Radios. CICC 2006: 789-796 - 2005
- [j13]Khurram Muhammad, Robert Bogdan Staszewski
Digital RF processing: toward low-cost reconfigurable radios. IEEE Commun. Mag. 43(8): 105-113 (2005) - [j12]Robert Bogdan Staszewski
A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones. IEEE J. Solid State Circuits 40(11): 2203-2211 (2005) - [j11]Robert Bogdan Staszewski
All-digital PLL and transmitter for mobile phones. IEEE J. Solid State Circuits 40(12): 2469-2482 (2005) - [j10]Robert Bogdan Staszewski
Phase-domain all-digital phase-locked loop. IEEE Trans. Circuits Syst. II Express Briefs 52-II(3): 159-163 (2005) - [j9]Robert Bogdan Staszewski
Event-driven Simulation and modeling of phase noise of an RF oscillator. IEEE Trans. Circuits Syst. I Regul. Pap. 52-I(4): 723-733 (2005) - [j8]Robert Bogdan Staszewski
Direct frequency modulation of an ADPLL for bluetooth/GSM with injection pulling elimination. IEEE Trans. Circuits Syst. II Express Briefs 52-II(6): 339-343 (2005) - [j7]Robert Bogdan Staszewski
SoC with an integrated DSP and a 2.4-GHz RF transmitter. IEEE Trans. Very Large Scale Integr. Syst. 13(11): 1253-1265 (2005) - [c12]Khurram Waheed, Robert Bogdan Staszewski
Characterization of deep-submicron varactor mismatches in a digitally controlled oscillator. CICC 2005: 605-608 - [c11]Khurram Muhammad, Yo-Chuol Ho, Terry Mayhugh Jr., Chih-Ming Hung
A discrete time quad-band GSM/GPRS receiver in a 90nm digital CMOS process. CICC 2005: 809-812 - [c10]Robert Bogdan Staszewski
Digital RF processor (DRP™) for cellular phones. ICCAD 2005: 122-129 - [c9]Robert Bogdan Staszewski
Sigma-Delta Noise Shaping for Digital-to-Frequency and Digital-to-RF-Amplitude Conversion. IWSOC 2005: 154-159 - [c8]Robert Bogdan Staszewski
Digital RF Processing Techniques for SoC Radios, invited. IWSOC 2005: 217-222 - [c7]Robert Bogdan Staszewski
VHDL Simulation and Modeling of an All-Digital RF Transmitter. IWSOC 2005: 233-238 - 2004
- [j6]Robert Bogdan Staszewski
All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS. IEEE J. Solid State Circuits 39(12): 2278-2291 (2004) - [c6]Jinseok Koh, Khurram Muhammad, Robert Bogdan Staszewski
A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process. CICC 2004: 535-538 - [c5]Khurram Muhammad, Robert Bogdan Staszewski
Direct RF sampling mixer with recursive filtering in charge domain. ISCAS (1) 2004: 577-580 - [c4]Robert Bogdan Staszewski, Chan Fernando, Poras T. Balsara:
Event-driven simulation and modeling of an RF oscillator. ISCAS (4) 2004: 641-644 - 2003
- [j5]Robert Bogdan Staszewski
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 50(11): 815-828 (2003) - [j4]Robert Bogdan Staszewski
Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation. IEEE Trans. Circuits Syst. II Express Briefs 50(11): 887-892 (2003) - [c3]Robert Bogdan Staszewski
Just-in-time gain estimation of an RF digitally-controlled oscillator. CICC 2003: 571-574 - 2001
- [j3]Khurram Muhammad, Robert Bogdan Staszewski
Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 42-51 (2001) - [c2]Khurram Muhammad, Robert Bogdan Staszewski, Poras T. Balsara:
Challenges in integrated CMOS transceivers for short distance wireless. ACM Great Lakes Symposium on VLSI 2001: 45-50 - 2000
- [j2]Robert Bogdan Staszewski
A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels. IEEE J. Solid State Circuits 35(8): 1205-1210 (2000) - [c1]Khurram Muhammad, Robert Bogdan Staszewski
Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels. ISLPED 2000: 262-267
1990 – 1999
- 1997
- [j1]Sami Kiriaki, T. Lakshmi Viswanathan, Gennady Feygin, Robert Bogdan Staszewski, Richard Pierson, Bill Krenik, Michiel de Wit, Krishnaswamy Nagaraj:
A 160-MHz analog equalizer for magnetic disk read Channel. IEEE J. Solid State Circuits 32(11): 1858-1865 (1997)
Coauthor Index
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last updated on 2025-03-18 20:43 CET by the dblp team
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