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Damu Radhakrishnan
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2000 – 2009
- 2009
- [j3]Bijoy Antony Jose, Damu Radhakrishnan:
Redundant binary partial product generators for compact accumulation in Booth multipliers. Microelectron. J. 40(11): 1606-1612 (2009) - 2008
- [j2]Yu Shen Lin, Damu Radhakrishnan:
Delay Efficient 32-Bit Carry-Skip Adder. VLSI Design 2008: 218565:1-218565:8 (2008) - 2006
- [c16]Yu Shen Lin, Damu Radhakrishnan:
Delay Efficient 32-bit Carry-Skip Adder. ICECS 2006: 506-509 - [c15]Bijoy Antony Jose, Damu Radhakrishnan:
Delay Optimized Redundant Binary Adders. ICECS 2006: 514-517 - 2004
- [c14]Smith Castillo, Naveen K. Samala, Kerron Manwaring, Baback A. Izadi, Damu Radhakrishnan:
Experimental Analysis of Batteries Under Continuous and Intermittent Operations. ESA/VLSI 2004: 18-24 - [c13]Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi:
A Low Energy Deep Sub-Micron Bus Coding Technique. ESA/VLSI 2004: 25-30 - [c12]Yong Liu, Edmund Ming-Kit Lai, A. Benjamin Premkumar, Damu Radhakrishnan:
A Low-Power Pipelined Implementation of 2D Discrete Wavelet Transform. ESA/VLSI 2004: 40-46 - [c11]Rakesh Menon, Sarita Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi:
Switching Activity Minimization in Combinational Logic Design. ESA/VLSI 2004: 47-53 - [c10]Jayapreetha Natesan, Damu Radhakrishnan:
A Novel Bus Encoding Technique for Low Power VLSI. ESA/VLSI 2004: 54-62 - [c9]Jayapreetha Natesan, Damu Radhakrishnan:
Shift Invert Coding (SINV) for Low Power VLSI. DSD 2004: 190-194 - 2003
- [c8]Rakesh Menon, Sarita Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi:
Power Optimized Combinational Logic Design. Embedded Systems and Applications 2003: 223-227 - [c7]Saumya Uppaluri, Baback A. Izadi, Damu Radhakrishnan:
Low-Power Dynamic Scheduling in Heterogeneous Systems. Embedded Systems and Applications 2003: 261-267 - 2001
- [c6]Adimathara P. Preethy, Damu Radhakrishnan, Amos Omondi:
A high performance RNS multiply-accumulate unit. ACM Great Lakes Symposium on VLSI 2001: 145-148 - [c5]Adimathara P. Preethy, Damu Radhakrishnan, Amos Omondi:
Fault-tolerance scheme for an RNS MAC: performance and cost analysis. ISCAS (2) 2001: 717-720 - 2000
- [c4]Damu Radhakrishnan:
Pass logic circuits with reduced switching activity for low power DSP processors. ICASSP 2000: 3327-3330
1990 – 1999
- 1999
- [j1]Damu Radhakrishnan, Adimathara P. Preethy:
A Parallel Approach to Direct Analog-to-Residue Conversion. Inf. Process. Lett. 69(5): 249-252 (1999) - 1998
- [c3]Damu Radhakrishnan, Adimathara P. Preethy:
A new approach to data conversion: direct analog-to-residue converter. ICASSP 1998: 3013-3016 - 1990
- [c2]Damu Radhakrishnan, Taejin Pyon:
Fault tolerance in RNS: an efficient approach. ICCD 1990: 41-44
1980 – 1989
Coauthor Index
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