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Tianyue Lu
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2020 – today
- 2024
- [j2]Luming Wang
, Xu Zhang
Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access. ACM Trans. Archit. Code Optim. 21(3): 55:1-55:28 (2024) - [i6]Luming Wang, Xu Zhang, Songyue Wang, Zhuolun Jiang, Tianyue Lu, Mingyu Chen, Siwei Luo, Keji Huang:
Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access. CoRR abs/2404.11044 (2024) - 2023
- [c12]Xu Zhang
Rethinking Design Paradigm of Graph Processing System with a CXL-like Memory Semantic Fabric. CCGrid 2023: 25-35 - [c11]Haifeng Li, Ke Liu, Ting Liang, Zuojun Li, Tianyue Lu, Yisong Chang, Hui Yuan, Yinben Xia, Yungang Bao, Mingyu Chen, Yizhou Shan:
MARB: Bridge the Semantic Gap between Operating System and Application Memory Access Behavior. DATE 2023: 1-6 - [c10]Haifeng Li, Ke Liu, Ting Liang, Zuojun Li, Tianyue Lu, Hui Yuan, Yinben Xia, Yungang Bao, Mingyu Chen, Yizhou Shan:
HoPP: Hardware-Software Co-Designed Page Prefetching for Disaggregated Memory. HPCA 2023: 1168-1181 - [c9]Xu Zhang, Tianyue Lu, Yisong Chang, Ke Zhang, Mingyu Chen:
Morpheus: An Adaptive DRAM Cache with Online Granularity Adjustment for Disaggregated Memory. ICCD 2023: 134-141 - [i5]Yue Jin, Yibin Xu, Chengyuan Yang, Han Wang, Tianyi Huang, Tianyue Lu, Mingyu Chen:
DASICS: Enhancing Memory Protection with Dynamic Compartmentalization. CoRR abs/2310.06435 (2023) - 2022
- [c8]Xu Zhang
GraFF: A Multi-FPGA System with Memory Semantic Fabric for Scalable Graph Processing. FPT 2022: 1-2 - 2021
- [c7]Haiyang Pan, Yuhang Liu, Tianyue Lu, Mingyu Chen:
LSP: Collective Cross-Page Prefetching for NVM. DATE 2021: 501-506 - [i4]Luming Wang, Xu Zhang, Tianyue Lu, Mingyu Chen:
Asynchronous Memory Access Unit for General Purpose Processors. CoRR abs/2112.13306 (2021) - 2020
- [i3]Tianyue Lu, Haiyang Pan, Mingyu Chen:
System measurement of Intel AEP Optane DIMM. CoRR abs/2009.14469 (2020)
2010 – 2019
- 2019
- [c6]Haiyang Pan, Yuhang Liu, Tianyue Lu, Mingyu Chen:
Characterizations and Architectural Implications of NVM's External DRAM Cache. HPCC/SmartCity/DSS 2019: 373-380 - [c5]Haifeng Li, Tianyue Lu, Yuhang Liu, Mingyu Chen:
Make Page Coloring more Efficient on Slice-Based Three-Level Cache. ICPADS 2019: 310-317 - 2017
- [c4]Tianyue Lu, Yuhang Liu, Haiyang Pan, Mingyu Chen:
TDV Cache: Organizing Off-Chip DRAM Cache of NVMM from a Fusion Perspective. ICCD 2017: 65-72 - [c3]Tianyue Lu, Yuhang Liu, Mingyu Chen:
Fine-Grained Data Committing for Persistent Memory. ISPA/IUCC 2017: 438-443 - 2016
- [c2]Zehan Cui, Tianyue Lu, Sally A. McKee, Mingyu Chen, Haiyang Pan, Yuan Ruan:
Twin-Load: Bridging the Gap between Conventional Direct-Attached and Buffer-on-Board Memory Systems. MEMSYS 2016: 164-176 - 2015
- [i2]Zehan Cui, Tianyue Lu, Haiyang Pan, Sally A. McKee, Mingyu Chen:
Twin-Load: Building a Scalable Memory System over the Non-Scalable Interface. CoRR abs/1505.03476 (2015) - 2014
- [j1]Licheng Chen, Mingyu Chen, Yuan Ruan, Yongbing Huang, Zehan Cui, Tianyue Lu, Yungang Bao:
MIMS: Towards a Message Interface Based Memory System. J. Comput. Sci. Technol. 29(2): 255-272 (2014) - [c1]Tianyue Lu, Licheng Chen, Mingyu Chen:
Achieving efficient packet-based memory system by exploiting correlation of memory requests. DATE 2014: 1-6 - 2013
- [i1]Licheng Chen, Tianyue Lu, Yanan Wang, Mingyu Chen, Yuan Ruan, Zehan Cui, Yongbing Huang, Mingyang Chen, Jiutian Zhang, Yungang Bao:
MIMS: Towards a Message Interface based Memory System. CoRR abs/1301.0051 (2013)
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