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Tomohiro Ueno
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2020 – today
- 2025
- [j10]Franck Cappello
, Mario C. Acosta, Emmanuel Agullo, Hartwig Anzt, Jon Calhoun, Sheng Di, Luc Giraud, Thomas Grützmacher, Sian Jin, Kentaro Sano, Kento Sato, Amarjit Singh, Dingwen Tao, Jiannan Tian, Tomohiro Ueno, Robert Underwood, Frédéric Vivien, Xavier Yepes, Kazutomo Yoshii, Boyuan Zhang:
Multifacets of lossy compression for scientific data in the Joint-Laboratory of Extreme Scale Computing. Future Gener. Comput. Syst. 163: 107323 (2025) - 2024
- [j9]Juan Miguel De Haro Ruiz
Automated parallel execution of distributed task graphs with FPGA clusters. Future Gener. Comput. Syst. 160: 808-824 (2024) - [c32]Tomohiro Ueno
Flexible Systolic Array Platform on Virtual 2-D Multi-FPGA Plane. HPC Asia 2024: 84-94 - [c31]Daiki Furukawa, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno
HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA Accelerator. ICCE 2024: 1-6 - [c30]Haruto Ikehara, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno
A Productive HLS Simulation Approach for Multi-FPGA Systems. ICCE 2024: 1-2 - 2023
- [j8]Tomohiro Ueno
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster. ACM Trans. Reconfigurable Technol. Syst. 16(2): 25:1-25:32 (2023) - [c29]Kentaro Sano
ESSPER: Elastic and Scalable FPGA-Cluster System for High-Performance Reconfigurable Computing with Supercomputer Fugaku. HPC Asia 2023: 140-150 - [c28]Boma A. Adhi, Carlos Cortes, Emanuele Del Sozzo
Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC. IPDPS Workshops 2023: 452-459 - [c27]Kazutomo Yoshii
Streaming Hardware Compressor Generator Framework. SC Workshops 2023: 289-297 - [c26]Kazutomo Yoshii
Hardware Specialization: Estimating Monte Carlo Cross-Section Lookup Kernel Performance and Area. SC Workshops 2023: 1274-1278 - 2022
- [c25]Boma A. Adhi
Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage. FPT 2022: 1-4 - [c24]Kentaro Sano, Atsushi Koshiba, Takaaki Miyajima, Tomohiro Ueno
ESSPER: Elastic and Scalable System for High-Performance Reconfigurable Computing with Software-bridged APIs. FPT 2022: 1 - [c23]Tatsuma Mori, Daiki Furukawa, Keigo Motoyoshi, Haruto Ikehara, Kaito Ohira, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno
Stream Computation of 3D Approximate Convex Hulls with an FPGA. HEART 2022: 69-75 - [c22]Tomohiro Ueno
FPGA-Dedicated Network vs. Server Network for Pipelined Computing with Multiple FPGAs. HEART 2022: 90-91 - 2021
- [c21]Tomohiro Ueno
Virtual Circuit-Switching Network with Flexible Topology for High-Performance FPGA Cluster. ASAP 2021: 41-48 - 2020
- [c20]Antoniette Mondigo
Comparison of Direct and Indirect Networks for High-Performance FPGA Clusters. ARC 2020: 314-329 - [c19]Norihisa Fujita, Ryohei Kobayashi
Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA. IPDPS Workshops 2020: 450-459
2010 – 2019
- 2019
- [j7]Antoniette Mondigo
Scalability Analysis of Deeply Pipelined Tsunami Simulation with Multiple FPGAs. IEICE Trans. Inf. Syst. 102-D(5): 1029-1036 (2019) - [c18]Tomohiro Ueno
Hybrid Network Utilization for Efficient Communication in a Tightly Coupled FPGA Cluster. FPT 2019: 363-366 - 2018
- [c17]Tomohiro Ueno
Performance Analysis of Hardware-Based Numerical Data Compression on Various Data Formats. DCC 2018: 345-354 - [c16]Jinpil Lee, Tomohiro Ueno
High-productivity Programming and Optimization Framework for Stream Processing on FPGA. HEART 2018: 5:1-5:6 - 2017
- [j6]Rui Wu
64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. IEEE J. Solid State Circuits 52(11): 2871-2891 (2017) - [j5]Tomohiro Ueno
Bandwidth Compression of Floating-Point Numerical Data Streams for FPGA-Based High-Performance Computing. ACM Trans. Reconfigurable Technol. Syst. 10(3): 18:1-18:22 (2017) - [c15]Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz
Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. ASICON 2017: 1025-1028 - [c14]Kentaro Sano, Shin Abiko, Tomohiro Ueno
FPGA-based Stream Computing for High-Performance N-Body Simulation using Floating-Point DSP Blocks. HEART 2017: 16:1-16:6 - [c13]Antoniette Mondigo
Design and scalability analysis of bandwidth-compressed stream computing with multiple FPGAs. ReCoSoC 2017: 1-8 - 2016
- [j4]Dongsheng Yang, Tomohiro Ueno, Wei Deng, Yuki Terashima, Kengo Nakata, Aravind Tharayil Narayanan
A 0.0055mm2 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI. IEICE Trans. Electron. 99-C(6): 632-640 (2016) - [j3]Teerachot Siriburanon
A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. IEEE J. Solid State Circuits 51(6): 1385-1397 (2016) - [c12]Rui Wu, Jian Pang, Yuuki Seo, Kento Kimura, Seitaro Kawai, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada
An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation. A-SSCC 2016: 109-112 - [c11]Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon
13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. ISSCC 2016: 248-249 - 2015
- [j2]Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon
A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. IEEE J. Solid State Circuits 50(1): 68-80 (2015) - [c10]Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon
An HDL-synthesized gated-edge-injection PLL with a current output DAC. ASP-DAC 2015: 2-3 - [c9]Teerachot Siriburanon
A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. ASP-DAC 2015: 42-43 - [c8]Teerachot Siriburanon
25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. ISSCC 2015: 1-3 - [c7]Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada
19.5 An HCI-healing 60GHz CMOS transceiver. ISSCC 2015: 1-3 - 2014
- [c6]Tomohiro Ueno
Bandwidth compression of multiple numerical data streams for high performance custom computing. ASAP 2014: 190-191 - [c5]Yuya Umemoto, Mai Murashima, Tomohiro Ueno, Naozo Sugimoto:
Effects of densely sampled dipole field on quantitative susceptibility mapping. EMBC 2014: 2352-2355 - [c4]Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon
15.1 A 0.0066mm2 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique. ISSCC 2014: 266-267 - [c3]Kenichi Okada
20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding. ISSCC 2014: 346-347 - [i1]Kentaro Sano, Hayato Suzuki, Ryo Ito, Tomohiro Ueno, Satoru Yamamoto:
Stream Processor Generator for HPC to Embedded Applications on FPGA-based System Platform. CoRR abs/1408.5386 (2014) - 2013
- [j1]Kentaro Sano, Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Ryo Ito, Tomohiro Ueno
Efficient custom computing of fully-streamed lattice boltzmann method on tightly-coupled FPGA cluster. SIGARCH Comput. Archit. News 41(5): 47-52 (2013) - [c2]Tomohiro Ueno
Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-Based Custom Computing. ARC 2013: 90-102 - [c1]Mai Murashima, Tomohiro Ueno, Naozo Sugimoto:
Effective digitized spatial size of unit dipole field in Quantitative Susceptibility Mapping. EMBC 2013: 1049-1052
Coauthor Index
aka: Kenichi Okada
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