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2020 – today
- 2024
- [j13]Yongan Zhang
, Xiaofan Zhang, Pengfei Xu, Yang Zhao, Cong Hao
AutoAI2C: An Automated Hardware Generator for DNN Acceleration on Both FPGA and ASIC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(10): 3143-3156 (2024) - [j12]Nan Wu
Survey of Machine Learning for Software-assisted Hardware Design Verification: Past, Present, and Prospect. ACM Trans. Design Autom. Electr. Syst. 29(4): 1-42 (2024) - [j11]Jennifer Hasler
Programmable Analog System Benchmarks Leading to Efficient Analog Computation Synthesis. ACM Trans. Reconfigurable Technol. Syst. 17(1): 12:1-12:25 (2024) - [c69]Hanqiu Chen
ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model. DAC 2024: 106:1-106:6 - [c68]Rishov Sarkar, Rachel Paul, Cong Hao:
LightningSimV2: Faster and Scalable Simulation for High-Level Synthesis via Graph Compilation and Optimization. FCCM 2024: 104-114 - [c67]Rishov Sarkar, Cong Hao:
Ph.D. Project: Modernizing High-Level Hardware Design Workflows. FCCM 2024: 245-246 - [c66]Yuchen Xia, Jiho Kim, Yuhan Chen, Haojie Ye, Souvik Kundu, Cong Callie Hao, Nishil Talati:
Understanding the Performance and Estimating the Cost of LLM Fine-Tuning. IISWC 2024: 210-223 - [c65]Dongning Ma, Cong Hao, Xun Jiao:
Hyperdimensional Computing vs. Neural Networks: Comparing Architecture and Learning Process. ISQED 2024: 1-5 - [c64]Stefan Abi-Karam
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond. MLCAD 2024: 23:1-23:9 - [c63]Jingtian Dang, Jianming Tong, Anupam Golder, Cong Hao, Arijit Raychowdhury, Tushar Krishna:
Accurate Low-Degree Polynomial Approximation of Non-Polynomial Operators for Fast Private Inference in Homomorphic Encryption. MLSys 2024 - [i47]Rishov Sarkar, Rachel Paul, Cong Hao:
LightningSimV2: Faster and Scalable Simulation for High-Level Synthesis via Graph Compilation and Optimization. CoRR abs/2404.09471 (2024) - [i46]Stefan Abi-Karam, Rishov Sarkar, Allison Seigler, Sean Lowe, Zhigang Wei, Hanqiu Chen, Nanditha Rao, Lizy Kurian John, Aman Arora, Cong Hao:
HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond. CoRR abs/2405.00820 (2024) - [i45]Yuchen Xia, Jiho Kim, Yuhan Chen, Haojie Ye, Souvik Kundu, Cong Hao, Nishil Talati:
Understanding the Performance and Estimating the Cost of LLM Fine-Tuning. CoRR abs/2408.04693 (2024) - [i44]Hanqiu Chen, Yitu Wang, Luis Vitório Cargnini, Mohammadreza Soltaniyeh, Dongyang Li, Gongjin Sun, Pradeep Subedi, Andrew Chang, Yiran Chen, Cong Hao:
ICGMM: CXL-enabled Memory Expansion with Intelligent Caching Using Gaussian Mixture Model. CoRR abs/2408.05614 (2024) - [i43]Hanqiu Chen, Xuebin Yao, Pradeep Subedi, Cong Hao:
Residual-INR: Communication Efficient On-Device Learning Using Implicit Neural Representation. CoRR abs/2408.05617 (2024) - [i42]Cong Hao:
Exploring and Exploiting Runtime Reconfigurable Floating Point Precision in Scientific Computing: a Case Study for Solving PDEs. CoRR abs/2409.15073 (2024) - [i41]Yaoyao Long, Zhenming Liu, Cong Hao, Farrokh Ayazi:
MEMS Gyroscope Multi-Feature Calibration Using Machine Learning Technique. CoRR abs/2410.07519 (2024) - 2023
- [j10]Stefan Abi-Karam
GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization. Softw. Pract. Exp. 53(11): 212-218 (2023) - [j9]Nan Wu
IronMan-Pro: Multiobjective Design Space Exploration in HLS via Reinforcement Learning and Graph Neural Network-Based Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 900-913 (2023) - [c62]Yimeng Zhang
Data-Model-Circuit Tri-Design for Ultra-Light Video Intelligence on Edge Devices. ASP-DAC 2023: 745-750 - [c61]Nan Wu
Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks. DAC 2023: 1-6 - [c60]Akshay Karkal Kamath
M5: Multi-modal Multi-task Model Mapping on Multi-FPGA with Accelerator Configuration Search. DATE 2023: 1-6 - [c59]Rishov Sarkar
LightningSim: Fast and Accurate Trace-Based Simulation for High-Level Synthesis. FCCM 2023: 1-11 - [c58]Hanqiu Chen, Cong Hao:
DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network Inference. FCCM 2023: 195-201 - [c57]Hanqiu Chen, Cong Hao:
Hardware/Software Co-design for Machine Learning Accelerators. FCCM 2023: 233-235 - [c56]Rishov Sarkar
From Acceleration to Accelerating Acceleration: Modernizing the Accelerator Landscape using High-Level Synthesis. FCCM 2023: 236-238 - [c55]Stefan Abi-Karam
GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization. FPL 2023: 212-218 - [c54]Rishov Sarkar
FlowGNN: A Dataflow Architecture for Real-Time Workload-Agnostic Graph Neural Network Inference. HPCA 2023: 1099-1112 - [c53]Stefan Abi-Karam, Rishov Sarkar, Dejia Xu, Zhiwen Fan, Zhangyang Wang, Cong Hao:
INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation Processing. ICCAD 2023: 1-9 - [c52]Hanqiu Chen, Hang Yang, Stephen B. R. Fitzmeyer, Cong Hao:
Rapid-INR: Storage Efficient CPU-Free DNN Training Using Implicit Neural Representation. ICCAD 2023: 1-9 - [c51]Rishov Sarkar, Hanxue Liang, Zhiwen Fan, Zhangyang Wang, Cong Hao:
Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-Level Sparsity via Mixture-of-Experts. ICCAD 2023: 1-9 - [c50]Yuhong Li, Jiajie Li, Cong Hao, Pan Li, Jinjun Xiong, Deming Chen:
Extensible and Efficient Proxy for Neural Architecture Search. ICCV 2023: 6176-6187 - [c49]Lakshmi Sathidevi, Abhinav Sharma
PreAxC: Error Distribution Prediction for Approximate Computing Quality Control using Graph Neural Networks. ISQED 2023: 1-7 - [i40]Nan Wu, Yingjie Li, Cong Hao, Steve Dai, Cunxi Yu, Yuan Xie:
Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks. CoRR abs/2303.08256 (2023) - [i39]Stefan Abi-Karam
GNNBuilder: An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization. CoRR abs/2303.16459 (2023) - [i38]Hanqiu Chen, Cong Hao:
DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network Inference. CoRR abs/2304.06831 (2023) - [i37]Rishov Sarkar, Cong Hao:
LightningSim: Fast and Accurate Trace-Based Simulation for High-Level Synthesis. CoRR abs/2304.11219 (2023) - [i36]Rishov Sarkar
Edge-MoE: Memory-Efficient Multi-Task Vision Transformer Architecture with Task-level Sparsity via Mixture-of-Experts. CoRR abs/2305.18691 (2023) - [i35]Hanqiu Chen, Hang Yang, Stephen B. R. Fitzmeyer, Cong Hao:
Rapid-INR: Storage Efficient CPU-free DNN Training Using Implicit Neural Representation. CoRR abs/2306.16699 (2023) - [i34]Stefan Abi-Karam
INR-Arch: A Dataflow Architecture and Compiler for Arbitrary-Order Gradient Computations in Implicit Neural Representation Processing. CoRR abs/2308.05930 (2023) - 2022
- [c48]Zishen Wan, Ashwin Sanjay Lele, Bo Yu, Shaoshan Liu, Yu Wang, Vijay Janapa Reddi, Cong Hao, Arijit Raychowdhury:
Robotic Computing on FPGAs: Current Progress, Research Challenges, and Opportunities. AICAS 2022: 291-295 - [c47]Nan Wu
LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models. ASAP 2022: 11-18 - [c46]Hanqiu Chen, Cong Hao:
Mask-Net: A Hardware-efficient Object Detection Network with Masked Region Proposals. ASAP 2022: 131-138 - [c45]Nan Wu
High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancing. DAC 2022: 49-54 - [c44]Xinyi Zhang, Cong Hao, Peipei Zhou
H2H: heterogeneous model to heterogeneous system mapping with computation and communication awareness. DAC 2022: 601-606 - [c43]Hanchen Ye
ScaleHLS: A New Scalable High-Level Synthesis Framework on Multi-Level Intermediate Representation. HPCA 2022: 741-755 - [c42]Nan Wu
AI-assisted Synthesis in Next Generation EDA: Promises, Challenges, and Prospects. ICCD 2022: 207-214 - [c41]Hanqiu Chen, Yahya Alhinai, Yihan Jiang, Eunjee Na, Cong Hao:
Bottleneck Analysis of Dynamic Graph Neural Network Inference on CPU and GPU. IISWC 2022: 130-145 - [c40]Qing Lu
RT-DNAS: Real-Time Constrained Differentiable Neural Architecture Search for 3D Cardiac Cine MRI Segmentation. MICCAI (5) 2022: 602-612 - [c39]Haoyu Wang, Nan Wu, Hang Yang, Cong Hao, Pan Li:
Unsupervised Learning for Combinatorial Optimization with Principled Objective Relaxation. NeurIPS 2022 - [c38]Hanxue Liang, Zhiwen Fan, Rishov Sarkar, Ziyu Jiang, Tianlong Chen, Kai Zou, Yu Cheng, Cong Hao, Zhangyang Wang:
M³ViT: Mixture-of-Experts Vision Transformer for Efficient Multi-task Learning with Model-Accelerator Co-design. NeurIPS 2022 - [i33]Nan Wu, Hang Yang, Yuan Xie, Pan Li, Cong Hao:
High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing. CoRR abs/2201.06848 (2022) - [i32]Nan Wu, Jiwon Lee, Yuan Xie, Cong Hao:
Hybrid Graph Models for Logic Optimization via Spatio-Temporal Information. CoRR abs/2201.08455 (2022) - [i31]Stefan Abi-Karam, Yuqi He, Rishov Sarkar, Lakshmi Sathidevi, Zihang Qiao, Cong Hao:
GenGNN: A Generic FPGA Framework for Graph Neural Network Acceleration. CoRR abs/2201.08475 (2022) - [i30]Eric Qin, Raveesh Garg, Abhimanyu Bambhaniya, Michael Pellauer, Angshuman Parashar, Sivasankaran Rajamanickam, Cong Hao, Tushar Krishna:
Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity. CoRR abs/2201.08916 (2022) - [i29]Rishov Sarkar, Stefan Abi-Karam, Yuqi He, Lakshmi Sathidevi
FlowGNN: A Dataflow Architecture for Universal Graph Neural Network Inference via Multi-Queue Streaming. CoRR abs/2204.13103 (2022) - [i28]Xinyi Zhang, Cong Hao, Peipei Zhou, Alex K. Jones
H2H: Heterogeneous Model to Heterogeneous System Mapping with Computation and Communication Awareness. CoRR abs/2204.13852 (2022) - [i27]Zishen Wan, Ashwin Sanjay Lele, Bo Yu, Shaoshan Liu, Yu Wang, Vijay Janapa Reddi, Cong Hao, Arijit Raychowdhury:
Robotic Computing on FPGAs: Current Progress, Research Challenges, and Opportunities. CoRR abs/2205.07149 (2022) - [i26]Xiaofan Zhang, Yao Chen, Cong Hao, Sitao Huang, Yuhong Li, Deming Chen:
Efficient Machine Learning, Compilers, and Optimizations for Embedded Systems. CoRR abs/2206.03326 (2022) - [i25]Qing Lu, Xiaowei Xu, Shunjie Dong, Cong Hao, Lei Yang, Cheng Zhuo, Yiyu Shi:
RT-DNAS: Real-time Constrained Differentiable Neural Architecture Search for 3D Cardiac Cine MRI Segmentation. CoRR abs/2206.04682 (2022) - [i24]Haoyu Wang, Nan Wu, Hang Yang, Cong Hao, Pan Li:
Unsupervised Learning for Combinatorial Optimization with Principled Objective Relaxation. CoRR abs/2207.05984 (2022) - [i23]Hanqiu Chen, Yahya Alhinai, Yihan Jiang, Eunjee Na, Cong Hao:
Bottleneck Analysis of Dynamic Graph Neural Network Inference on CPU and GPU. CoRR abs/2210.03900 (2022) - [i22]Yimeng Zhang, Akshay Karkal Kamath, Qiucheng Wu, Zhiwen Fan, Wuyang Chen, Zhangyang Wang, Shiyu Chang, Sijia Liu, Cong Hao:
Data-Model-Circuit Tri-Design for Ultra-Light Video Intelligence on Edge Devices. CoRR abs/2210.08578 (2022) - [i21]Hanxue Liang, Zhiwen Fan, Rishov Sarkar, Ziyu Jiang, Tianlong Chen, Kai Zou, Yu Cheng, Cong Hao, Zhangyang Wang:
M3ViT: Mixture-of-Experts Vision Transformer for Efficient Multi-task Learning with Model-Accelerator Co-design. CoRR abs/2210.14793 (2022) - 2021
- [j8]Cong Hao, Jordan Dotzel
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Codesign. IEEE Des. Test 38(4): 7-26 (2021) - [j7]Jianwei Zheng
Improving the Generalization Ability of Deep Neural Networks for Cross-Domain Visual Recognition. IEEE Trans. Cogn. Dev. Syst. 13(3): 607-620 (2021) - [j6]Cheng Gong
VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization. IEEE Trans. Computers 70(5): 696-710 (2021) - [c37]Cong Hao, Deming Chen:
Software/Hardware Co-design for Multi-modal Multi-task Learning in Autonomous Systems. AICAS 2021: 1-5 - [c36]Xinheng Liu, Yao Chen
WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs. ASAP 2021: 258-265 - [c35]Lixiang Li, Yao Chen
MELOPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank. DAC 2021: 601-606 - [c34]Dongning Ma, Rahul Thapa, Xingjian Wang, Xun Jiao, Cong Hao:
Workload-Aware Approximate Computing Configuration. DATE 2021: 920-925 - [c33]Nan Wu
IRONMAN: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning. ACM Great Lakes Symposium on VLSI 2021: 39-44 - [c32]Yao Chen
3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low Bitwidth Quantization, and Ultra-Low Latency Acceleration. ACM Great Lakes Symposium on VLSI 2021: 157-162 - [c31]Chaojian Li, Zhongzhi Yu, Yonggan Fu, Yongan Zhang, Yang Zhao
HW-NAS-Bench: Hardware-Aware Neural Architecture Search Benchmark. ICLR 2021 - [c30]Susheel Suresh, Pan Li, Cong Hao, Jennifer Neville:
Adversarial Graph Augmentation to Improve Graph Contrastive Learning. NeurIPS 2021: 15920-15933 - [c29]Yuhong Li, Cong Hao, Pan Li, Jinjun Xiong, Deming Chen:
Generic Neural Architecture Search via Regression. NeurIPS 2021: 20476-20490 - [i20]Nan Wu
IronMan: GNN-assisted Design Space Exploration in High-Level Synthesis via Reinforcement Learning. CoRR abs/2102.08138 (2021) - [i19]Cong Hao, Jordan Dotzel, Jinjun Xiong, Luca Benini, Zhiru Zhang, Deming Chen:
Enabling Design Methodologies and Future Trends for Edge AI: Specialization and Co-design. CoRR abs/2103.15750 (2021) - [i18]Kaiqi Zhang, Cole Hawkins, Xiyuan Zhang, Cong Hao, Zheng Zhang:
On-FPGA Training with Ultra Memory Reduction: A Low-Precision Tensor Method. CoRR abs/2104.03420 (2021) - [i17]Cong Hao, Deming Chen:
Software/Hardware Co-design for Multi-modal Multi-task Learning in Autonomous Systems. CoRR abs/2104.04000 (2021) - [i16]Lixiang Li, Yao Chen, Zacharie Zirnheld, Pan Li, Cong Hao:
MELOPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank. CoRR abs/2104.09616 (2021) - [i15]Yao Chen, Cole Hawkins, Kaiqi Zhang, Zheng Zhang, Cong Hao:
3U-EdgeAI: Ultra-Low Memory Training, Ultra-Low BitwidthQuantization, and Ultra-Low Latency Acceleration. CoRR abs/2105.06250 (2021) - [i14]Susheel Suresh, Pan Li, Cong Hao, Jennifer Neville:
Adversarial Graph Augmentation to Improve Graph Contrastive Learning. CoRR abs/2106.05819 (2021) - [i13]Xinheng Liu, Yao Chen, Cong Hao, Ashutosh Dhar, Deming Chen:
WinoCNN: Kernel Sharing Winograd Systolic Array for Efficient Convolutional Neural Network Acceleration on FPGAs. CoRR abs/2107.04244 (2021) - [i12]Hanchen Ye, Cong Hao, Jianyi Cheng, Hyunmin Jeong, Jack Huang, Stephen Neuendorffer, Deming Chen:
ScaleHLS: Scalable High-Level Synthesis through MLIR. CoRR abs/2107.11673 (2021) - [i11]Yuhong Li, Cong Hao, Pan Li, Jinjun Xiong, Deming Chen:
Generic Neural Architecture Search via Regression. CoRR abs/2108.01899 (2021) - [i10]Nan Wu, Huake He, Yuan Xie, Pan Li, Cong Hao:
Program-to-Circuit: Exploiting GNNs for Program Representation and Circuit Translation. CoRR abs/2109.06265 (2021) - 2020
- [c28]Yuhong Li, Cong Hao, Xiaofan Zhang, Xinheng Liu, Yao Chen
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions. DAC 2020: 1-6 - [c27]Pengfei Xu, Xiaofan Zhang, Cong Hao, Yang Zhao
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs. FPGA 2020: 40-50 - [c26]Cong Hao, Yao Chen
Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices. ACM Great Lakes Symposium on VLSI 2020: 283-290 - [c25]Xiaofan Zhang, Haoming Lu, Cong Hao, Jiachen Li, Bowen Cheng, Yuhong Li, Kyle Rupnow, Jinjun Xiong, Thomas S. Huang, Honghui Shi, Wen-Mei Hwu, Deming Chen:
SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems. MLSys 2020 - [i9]Pengfei Xu, Xiaofan Zhang, Cong Hao, Yang Zhao, Yongan Zhang, Yue Wang, Chaojian Li, Zetong Guan, Deming Chen, Yingyan Lin:
AutoDNNchip: An Automated DNN Chip Predictor and Builder for Both FPGAs and ASICs. CoRR abs/2001.03535 (2020) - [i8]Yuhong Li, Cong Hao, Xiaofan Zhang, Xinheng Liu, Yao Chen, Jinjun Xiong, Wen-Mei W. Hwu, Deming Chen:
EDD: Efficient Differentiable DNN Architecture and Implementation Co-search for Embedded AI Solutions. CoRR abs/2005.02563 (2020) - [i7]Cheng Gong, Yao Chen, Ye Lu, Tao Li, Cong Hao, Deming Chen:
VecQ: Minimal Loss DNN Model Compression With Vectorized Weight Quantization. CoRR abs/2005.08501 (2020) - [i6]Cong Hao, Yao Chen, Xiaofan Zhang, Yuhong Li, Jinjun Xiong, Wen-Mei Hwu, Deming Chen:
Effective Algorithm-Accelerator Co-design for AI Solutions on Edge Devices. CoRR abs/2010.07185 (2020)
2010 – 2019
- 2019
- [c24]Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong
FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge. DAC 2019: 206 - [c23]Yao Chen
Cloud-DNN: An Open Framework for Mapping DNN Models to Cloud FPGAs. FPGA 2019: 73-82 - [c22]Cong Hao, Yao Chen
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving. ICCAD 2019: 1-8 - [c21]Cheng Gong
µL2Q: An Ultra-Low Loss Quantization Method for DNN Compression. IJCNN 2019: 1-8 - [c20]Yao Chen
T-DLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGA. ISVLSI 2019: 13-18 - [c19]Cong Hao, Junli Gu, Deming Chen, Atif Sarwari, Zhijie Jin, Husam Abu-Haimed, Daryl Sew, Yuhong Li, Xinheng Liu, Bryan Wu, Dongdong Fu:
A Hybrid GPU + FPGA System Design for Autonomous Driving Cars. SiPS 2019: 121-126 - [i5]Cong Hao, Xiaofan Zhang, Yuhong Li, Sitao Huang, Jinjun Xiong, Kyle Rupnow, Wen-Mei Hwu, Deming Chen:
FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge. CoRR abs/1904.04421 (2019) - [i4]Xiaofan Zhang, Cong Hao, Yuhong Li, Yao Chen
A Bi-Directional Co-Design Approach to Enable Deep Learning on IoT Devices. CoRR abs/1905.08369 (2019) - [i3]Xiaofan Zhang, Cong Hao, Haoming Lu, Jiachen Li, Yuhong Li, Yuchen Fan, Kyle Rupnow, Jinjun Xiong, Thomas S. Huang, Honghui Shi, Wen-Mei Hwu, Deming Chen:
SkyNet: A Champion Model for DAC-SDC on Low Power Object Detection. CoRR abs/1906.10327 (2019) - [i2]Xiaofan Zhang, Haoming Lu, Cong Hao, Jiachen Li, Bowen Cheng, Yuhong Li, Kyle Rupnow, Jinjun Xiong, Thomas S. Huang, Honghui Shi, Wen-mei W. Hwu, Deming Chen:
SkyNet: a Hardware-Efficient Method for Object Detection and Tracking on Embedded Systems. CoRR abs/1909.09709 (2019) - [i1]Cong Hao, Yao Chen, Xinheng Liu, Atif Sarwari, Daryl Sew, Ashutosh Dhar, Bryan Wu, Dongdong Fu, Jinjun Xiong, Wen-Mei Hwu, Junli Gu, Deming Chen:
NAIS: Neural Architecture and Implementation Search and its Applications in Autonomous Driving. CoRR abs/1911.07446 (2019) - 2018
- [c18]Matej Kristan, Ales Leonardis, Jiri Matas
The Sixth Visual Object Tracking VOT2018 Challenge Results. ECCV Workshops (1) 2018: 3-53 - [c17]Sitao Huang, Mohamed El-Hadedy, Cong Hao, Qin Li, Vikram S. Mailthody
Triangle Counting and Truss Decomposition using FPGA. HPEC 2018: 1-7 - [c16]Rujie Lai, Yangyizhou Wang, Cong Hao, Takeshi Yoshimura:
Economical Smart Home Scheduling by Cuckoo Search optimization via Levy Flight. MWSCAS 2018: 1030-1033 - [c15]Yi Zhao
TSV Assignment of Thermal and Wirelength Optimization for 3D-IC Routing. PATMOS 2018: 155-162 - 2017
- [j5]Cong Hao, Takeshi Yoshimura:
An Efficient Multi-Level Algorithm for 3D-IC TSV Assignment. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(3): 776-784 (2017) - [j4]Cong Hao
A Unified Scheduling Approach for Power and Resource Optimization With Multiple Vdd or/and Vth in High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12): 2030-2043 (2017) - [j3]Cong Hao
Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 1140-1153 (2017) - [c14]Cong Hao, Takeshi Yoshimura:
Application of on-line machine learning in optimization algorithms: A case study for local search. CEEC 2017: 19-24 - [c13]Yangyizhou Wang, Cong Hao, Takeshi Yoshimura:
A particle swarm optimization and branch and bound based algorithm for economical smart home scheduling. MWSCAS 2017: 213-216 - [c12]Yuxin Qian, Cong Hao, Takeshi Yoshimura:
3D-IC signal TSV assignment for thermal and wirelength optimization. PATMOS 2017: 1-8 - 2016
- [j2]Nan Wang, Wei Zhong, Cong Hao, Song Chen
Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design. IEEE Trans. Very Large Scale Integr. Syst. 24(10): 3067-3079 (2016) - [c11]Jiayi Ma, Cong Hao, Wencan Zhang, Takeshi Yoshimura:
Power-efficient partitioning and cluster generation design for application-specific Network-on-Chip. ISOCC 2016: 83-84 - [c10]Cong Hao, Takeshi Yoshimura:
Economical smart home scheduling for single and multiple users. MWSCAS 2016: 1-4 - [c9]Hui Zhu, Cong Hao, Takeshi Yoshimura:
Thermal-aware floorplanning for NoC-sprinting. MWSCAS 2016: 1-4 - [c8]Cong Hao, Nan Ding, Takeshi Yoshimura:
An efficient algorithm for 3D-IC TSV assignment. NEWCAS 2016: 1-4 - 2015
- [c7]Cong Hao, Jianmo Ni, Hui-Tong Wang, Takeshi Yoshimura:
Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis. ASICON 2015: 1-4 - [c6]Jianmo Ni, Cong Hao, Nan Wang, Qian Ai, Takeshi Yoshimura:
Primal-dual method based simultaneous functional unit and register binding. ASICON 2015: 1-4 - 2014
- [j1]Nan Wang, Song Chen
Leakage Power Aware Scheduling in High-Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(4): 940-951 (2014) - 2013
- [c5]Cong Hao, Nan Wang, Song Chen
Interconnection allocation between functional units and registers in High-Level Synthesis. ASICON 2013: 1-4 - [c4]Nan Wang, Cong Hao, Nan Liu, Haoran Zhang, Takeshi Yoshimura:
Timing and resource constrained leakage power aware scheduling in high-level synthesis. ASICON 2013: 1-4 - [c3]Haoran Zhang, Cong Hao, Nan Wang, Song Chen
Power and resource aware scheduling with multiple voltages. ASICON 2013: 1-4 - [c2]Cong Hao, Song Chen
Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis. ASP-DAC 2013: 237-242 - 2012
- [c1]Cong Hao, Song Chen
Port assignment for interconnect reduction in high-level synthesis. VLSI-DAT 2012: 1-4
Coauthor Index
Rama Krishna Sai S. Gorthi
aka: Rama Krishna Sai Subrahmanyam Gorthi
aka: Gorthi R. K. Sai Subrahmanyam
aka: Rama Krishna Sai Subrahmanyam Gorthi
aka: Gorthi R. K. Sai Subrahmanyam
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last updated on 2024-12-23 19:31 CET by the dblp team
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