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René Kothe
2010 – 2019
- 2010
- [c10]René Kothe, Heinrich Theodor Vierhaus:
Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures. DSD 2010: 283-290
2000 – 2009
- 2008
- [j1]René Kothe, Heinrich Theodor Vierhaus:
A Scan Controller Concept for Low Power Scan Tests. J. Low Power Electron. 4(3): 420-428 (2008) - [c9]Heinrich Theodor Vierhaus, René Kothe:
Embedded Diagnostic Logic Test Exploiting Regularity. DSD 2008: 873-879 - 2007
- [c8]René Kothe, Heinrich Theodor Vierhaus:
Flip-Flops and Scan-Path Elements for Nanoelectronics. DDECS 2007: 307-312 - [c7]R. Frost, D. Rudolph, Christian Galke, René Kothe, Heinrich Theodor Vierhaus:
A Configurable Modular Test Processor and Scan Controller Architecture. IOLTS 2007: 277-284 - 2006
- [c6]Christian Galke, René Kothe, Heinrich Theodor Vierhaus:
Logic Self Repair. ARCS Workshops 2006: 36-44 - [c5]René Kothe, Christian Galke, Sabine Schultke, Henry Fröschke, Steffen Gaede, Heinrich Theodor Vierhaus:
Hardware/Software Based Hierarchical Self Test for SoCs. DDECS 2006: 159-160 - [c4]René Kothe, Heinrich Theodor Vierhaus, Torsten Coym, Wolfgang Vermeiren, Bernd Straube:
Embedded Self Repair by Transistor and Gate Level Reconfiguration. DDECS 2006: 210-215 - [c3]Christian Galke, René Kothe, Sabine Schultke, K. Winkler, Jeanette Honko, Heinrich Theodor Vierhaus:
Embedded Scan Test with Diagnostic Features for Self-Testing SoCs. IOLTS 2006: 181-182 - [c2]S. Habermann, René Kothe, Heinrich Theodor Vierhaus:
Built-in Self Repair by Reconfiguration of FPGAs. IOLTS 2006: 187-188 - 2005
- [c1]René Kothe, Christian Galke, Heinrich Theodor Vierhaus:
A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features. IOLTS 2005: 241-246
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