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R. Marimuthu 0001
Person information
- affiliation: Vellore Institute of Technology (VIT), School of Electrical Engineering, India
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2020 – today
- 2024
- [j5]V. Ramya
, R. Marimuthu
Integration of AC/DC With Multi Input Mode Selection Converter for Fast Charging of Battery in Electric Vehicles. IEEE Access 12: 127115-127126 (2024) - [j4]Piyush Kumar Sinha
Conglomeration of deep neural network and quantum learning for object detection: Status quo review. Knowl. Based Syst. 288: 111480 (2024)
2010 – 2019
- 2018
- [j3]R. Marimuthu, S. Balamurugan, Partha Sharathi Mallick:
Design of 5-3 multicolumn compressor for high performance multiplier. Int. J. Comput. Aided Eng. Technol. 10(5): 568-575 (2018) - [c4]Saurabh Kumar, R. Marimuthu
Design and Analysis of 4-Bit Squarer Circuit Using Minority and Majority Logic in MagCAD. SocProS (2) 2018: 409-417 - [c3]Raunak R. Lahoti, Shantanu Agarwal, S. Balamurugan, R. Marimuthu
Realization of 2-D DCT Using Adder Compressor. SocProS (2) 2018: 575-580 - [c2]Shantanu Agarwal, G. Harish, S. Balamurugan
Design of High Speed 5: 2 and 7: 2 Compressor Using Nanomagnetic Logic. VDAT 2018: 49-60 - 2017
- [j2]R. Marimuthu
Design and Analysis of Multiplier Using Approximate 15-4 Compressor. IEEE Access 5: 1027-1036 (2017) - 2012
- [j1]S. Balamurugan
Design of low power fixed-width multiplier with row bypassing. IEICE Electron. Express 9(20): 1568-1575 (2012) - [c1]S. Balamurugan
FPGA design and implementation of truncated multipliers using bypassing technique. ICACCI 2012: 1111-1117
Coauthor Index
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