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Xiao Liang Tan
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2010 – 2019
- 2017
- [j7]Dong Wang, Xiao Liang Tan, Pak Kwong Chan:
A 65-nm CMOS Constant Current Source With Reduced PVT Variation. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1373-1385 (2017) - 2016
- [j6]Dong Wang, Xiao Liang Tan, Pak Kwong Chan:
A Sub-1 V 100 mA Wide Capacitive Load Based Flipped Voltage Follower Low-Dropout Regulator Using Transient-Assisted Embedded Driving Stage. J. Low Power Electron. 12(1): 45-55 (2016) - [j5]Xiao Liang Tan, Pak Kwong Chan:
A Fully Integrated Point-of-Load Digital System Supply With PVT Compensation. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1421-1429 (2016) - [j4]Dong Wang, Xiao Liang Tan, Pak Kwong Chan:
A Performance-Aware MOSFET Threshold Voltage Measurement Circuit in a 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 24(4): 1430-1440 (2016) - [c2]Dong Wang, Xiao Liang Tan, Pak Kwong Chan:
A sub-1V wide-load-range LDO regulator with sustained transient efficiency. ISIC 2016: 1-4 - 2015
- [j3]Xiao Liang Tan, Pak Kwong Chan, Uday Dasgupta:
A Sub-1-V 65-nm MOS Threshold Monitoring-Based Voltage Reference. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2317-2321 (2015) - 2014
- [j2]Xiao Liang Tan, Sau Siong Chong, Pak Kwong Chan, Uday Dasgupta:
A LDO Regulator With Weighted Current Feedback Technique for 0.47 nF-10 nF Capacitive Load. IEEE J. Solid State Circuits 49(11): 2658-2672 (2014) - [j1]Xiao Liang Tan, Kuan Chuang Koay, Sau Siong Chong, Pak Kwong Chan:
A FVF LDO Regulator With Dual-Summed Miller Frequency Compensation for Wide Load Capacitance Range Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(5): 1304-1312 (2014) - [c1]Xiao Liang Tan, Pak Kwong Chan, Uday Dasgupta:
An asynchronous sub-two-step quantizer for continuous-time sigma-delta modulators. ISCAS 2014: 710-713
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