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Seyed Mohammad Ali Zeinolabedin
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2020 – today
- 2024
- [c15]Seyed Mohammad Ali Zeinolabedin, Matthieu Couriol, Pierre-Emmanuel Gaillardon:
Selecting IRN for AFE to Achieve Power-Area-Noise Efficiency in Next-Generation Neural Implants. MWSCAS 2024: 651-655 - 2023
- [c14]Liyuan Guo, Matthias Jobst
, Johannes Partzsch
A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI. AICAS 2023: 1-5 - [c13]Liyuan Guo, Seyed Mohammad Ali Zeinolabedin, Franz Marcus Schüffny, Annika Weiße, Stefan Scholze, Richard George, Johannes Partzsch
A 16-channel Real-time Adaptive Neural Signal Compression Engine in 22nm FDSOI. NEWCAS 2023: 1-5 - [c12]Franz Marcus Schüffny, Stefan Hänzsche, Stephan Henker, Seyed Mohammad Ali Zeinolabedin, Stefan Scholze, Sebastian Höppner, Richard Miru George, Christian Mayr:
A 3.3V Saturation-Aware Neurostimulator with Reset Functionality in 22 nm FDSOI. NEWCAS 2023: 1-5 - 2022
- [j8]Seyed Mohammad Ali Zeinolabedin
A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI. IEEE Trans. Biomed. Circuits Syst. 16(1): 94-107 (2022) - [j7]Franz Marcus Schüffny
An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 739-743 (2022) - [c11]Shengpeng Guo, Liyuan Guo, Seyed Mohammad Ali Zeinolabedin
Various Distance Metrics Evaluation on Neural Spike Classification. BioCAS 2022: 554-558 - [c10]Franz Marcus Schüffny, Stefan Hänzsche, Marc Berthel, Seyed Mohammad Ali Zeinolabedin
A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm. NorCAS 2022: 1-5 - [c9]Franz Marcus Schüffny, Sebastian Höppner, Seyed Mohammad Ali Zeinolabedin
How to design an input stage for neural recording system in 22 nm FDSOI. PRIME 2022: 297-300 - 2021
- [j6]Seyed Mohammad Ali Zeinolabedin
Real-time Hardware Implementation of ARM CoreSight Trace Decoder. IEEE Des. Test 38(1): 69-77 (2021) - [c8]Qier Ma, Liyuan Guo, Seyed Mohammad Ali Zeinolabedin
Ultra-low Power and Area-efficient Hardware Accelerator for Adaptive Neural Signal Compression. BioCAS 2021: 1-4 - [c7]Seyed Mohammad Ali Zeinolabedin
Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator. DATE 2021: 1606-1609 - 2020
- [j5]Anh-Tuan Do
Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding. IEEE Trans. Circuits Syst. II Express Briefs 67-II(10): 2154-2158 (2020)
2010 – 2019
- 2019
- [j4]Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin
An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 126-137 (2019) - 2016
- [j3]Seyed Mohammad Ali Zeinolabedin
Structuring of Contourlet Transform for Pipeline-Based Implementation. Circuits Syst. Signal Process. 35(3): 953-976 (2016) - [j2]Seyed Mohammad Ali Zeinolabedin
A Power and Area Efficient Ultra-Low Voltage Laplacian Pyramid Processing Engine With Adaptive Data Compression. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10): 1690-1700 (2016) - [c6]Seyed Mohammad Ali Zeinolabedin
Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS. APCCAS 2016: 734-735 - [c5]Anh-Tuan Do, Seyed Mohammad Ali Zeinolabedin
A 0.3 pJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications. A-SSCC 2016: 173-176 - [c4]Seyed Mohammad Ali Zeinolabedin
A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j1]Seyed Mohammad Ali Zeinolabedin
An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2408-2416 (2015) - [c3]Seyed Mohammad Ali Zeinolabedin
A 0.5V power and area efficient Laplacian Pyramid processing engine using FIFO with adaptive data compression. ESSCIRC 2015: 104-107 - [c2]Seyed Mohammad Ali Zeinolabedin
Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits. ISCAS 2015: 794-797 - 2014
- [c1]Seyed Mohammad Ali Zeinolabedin
An area- and power-efficient FIFO with error-reduced data compression for image/video processing. ISCAS 2014: 2277-2280
Coauthor Index
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last updated on 2024-10-11 17:24 CEST by the dblp team
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