A low-jitter phase-locked resonant clock generation and distribution scheme. - Mandal, Ayan; Bollapalli, Kalyana C.; Jayakumar, Nikhil; Khatri, Sunil P.; Mahapatra, Rabi N. (2013)

An Automated Approach for Minimum Jitter Buffered H-Tree Construction. - Mandal, Ayan; Jayakumar, Nikhil; Bollapalli, Kalyana C.; Khatri, Sunil P.; Mahapatra, Rabi N. (2011)

Implementing digital logic with sinusoidal supplies. - Bollapalli, Kalyana C.; Khatri, Sunil P.; Kish, Laszlo B. (2010)

Selective Forward Body Bias for High Speed and Low Power SRAMs. - Bollapalli, Kalyana C.; Garg, Rajesh; Gulati, Kanupriya; Khatri, Sunil P. (J. Low Power Electron., 2009)

Highly parallel decoding of space-time codes on graphics processing units. - Bollapalli, Kalyana C.; Wu, Yiyue; Gulati, Kanupriya; Khatri, Sunil P.; Calderbank, A. Robert (2009)

Low power and high performance sram design using bank-based selective forward body bias. - Bollapalli, Kalyana C.; Garg, Rajesh; Gulati, Kanupriya; Khatri, Sunil P. (2009)

A robust pulsed flip-flop and its use in enhanced scan design. - Kumar, Rajesh; Bollapalli, Kalyana C.; Garg, Rajesh; Soni, Tarun; Khatri, Sunil P. (2009)

On-chip bidirectional wiring for heavily pipelined systems using network coding. - Bollapalli, Kalyana C.; Garg, Rajesh; Gulati, Kanupriya; Khatri, Sunil P. (2009)

A PLL design based on a standing wave resonant oscillator. - Karkala, Vinay; Bollapalli, Kalyana C.; Garg, Rajesh; Khatri, Sunil P. (2009)