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Cédric Bourrasset
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2010 – 2019
- 2018
- [j5]Luca Maggiani
, Cédric Bourrasset, Jean-Charles Quinton
Bio-inspired heterogeneous architecture for real-time pedestrian detection applications. J. Real Time Image Process. 14(3): 535-548 (2018) - [c7]Cédric Bourrasset, France Boillod-Cerneux, Ludovic Sauge, Myrtille Deldossi, Francois Wellenreiter, Rajesh Bordawekar, Susan Malaika, Jean-Armand Broyelle, Marc West, Brian M. Belgodere:
Requirements for an Enterprise AI Benchmark. TPCTC 2018: 71-81 - 2017
- [j4]Kamel Abdelouahab
Tactics to Directly Map CNN Graphs on Embedded FPGAs. IEEE Embed. Syst. Lett. 9(4): 113-116 (2017) - [i3]Kamel Abdelouahab, Cédric Bourrasset, Maxime Pelcat, François Berry, Jean-Charles Quinton, Jocelyn Sérot:
A Holistic Approach for Optimizing DSP Block Utilization of a CNN implementation on FPGA. CoRR abs/1703.09779 (2017) - [i2]Kamel Abdelouahab, Maxime Pelcat, Jocelyn Sérot, François Berry, Cédric Bourrasset, Jean-Charles Quinton:
Hardware Automated Dataflow Deployment of CNNs. CoRR abs/1705.04543 (2017) - [i1]Kamel Abdelouahab, Maxime Pelcat, Cédric Bourrasset, François Berry, Jocelyn Sérot:
Tactics to Directly Map CNN graphs on Embedded FPGAs. CoRR abs/1712.04322 (2017) - 2016
- [b1]Cédric Bourrasset:
Le modèle flot de données appliqué à la synthèse haut-niveau pour le traitement d'images sur caméra intelligente à base de FPGA. Application aux systèmes d'apprentissage supervisés. (High level synthesis of dataflow programs for image processing on FPGA-based smart camera. Application to machine learning). Blaise Pascal University, Clermont-Ferrand, France, 2016 - [j3]Cédric Bourrasset, Luca Maggiani, Jocelyn Sérot, François Berry:
Dataflow object detection system for FPGA-based smart camera. IET Circuits Devices Syst. 10(4): 280-291 (2016) - [j2]Jocelyn Sérot, François Berry, Cédric Bourrasset:
High-level dataflow programming for real-time image processing on smart cameras. J. Real Time Image Process. 12(4): 635-647 (2016) - [c6]Kamel Abdelouahab
A Holistic Approach for Optimizing DSP Block Utilization of a CNN implementation on FPGA. ICDSC 2016: 69-75 - [c5]Maxime Pelcat, Cédric Bourrasset, Luca Maggiani, François Berry:
Design productivity of a high level synthesis compiler versus HDL. SAMOS 2016: 140-147 - 2015
- [j1]Luca Maggiani
HOG-Dot: A Parallel Kernel-Based Gradient Extraction for Embedded Image Processing. IEEE Signal Process. Lett. 22(11): 2132-2136 (2015) - [c4]Luca Maggiani
Parallel image gradient extraction core for FPGA-based smart cameras. ICDSC 2015: 128-133 - 2013
- [c3]Cédric Bourrasset, Luca Maggiani
DreamCAM: A FPGA-based platform for smart camera networks. ICDSC 2013: 1-2 - [c2]Cédric Bourrasset, Luca Maggiani, Jocelyn Sérot, François Berry, Paolo Pagano
Distributed FPGA-based smart camera architecture for computer vision applications. ICDSC 2013: 1-2 - [c1]Cédric Bourrasset, Jocelyn Sérot, François Berry:
FPGA-based smart camera mote for pervasive wireless network. ICDSC 2013: 1-6
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