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Shiheng Yang
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2020 – today
- 2024
- [j10]Yueduo Liu
, Zihao Zhu
A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 71(2): 515-525 (2024) - 2023
- [j9]Zehao Zhang, Shiheng Yang
On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up. IEEE Trans. Circuits Syst. II Express Briefs 70(1): 26-30 (2023) - [j8]Yuchen Wei
A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1248-1252 (2023) - 2022
- [j7]Yueduo Liu
Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. 69(2): 495-505 (2022) - [c8]Mingkang Zhang, Zihao Zhu, Yueduo Liu, Zehao Zhang, Rongxin Bao, Jiahui Lin, Haovu Zhuang, Jiaxin Liu, Xiong Zhou, Shiheng Yang, Qiang Li:
A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS. ICTA 2022: 36-37 - 2021
- [j6]Bojun Hu
Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs. IEEE Open J. Circuits Syst. 2: 304-310 (2021) - [j5]Shiheng Yang
A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3108-3112 (2021) - [c7]Xiaodan Zhou, Zehao Li, Yujie Wang, Xiong Zhou, Shiheng Yang, Jiaxin Liu, Qiang Li:
A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC. APCCAS 2021: 189-192 - [c6]Yan Zeng, Shiheng Yang, Yueduo Liu, Zehao Li, Wengang Huang, Xiaozong Huang, Xiong Zhou, Jiaxin Liu, Qiang Li:
A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration. A-SSCC 2021: 1-3 - [c5]Yueduo Liu, Zihao Zhu, Rongxin Bao, Shiheng Yang, Jiaxin Liu, Xiong Zhou, Qiang Li:
A Low-Power RC Oscillator with Offset and Path Delay Cancellation. ICTA 2021: 12-13 - 2020
- [j4]Zunsong Yang
A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector. IEEE Access 8: 2222-2232 (2020)
2010 – 2019
- 2019
- [j3]Shiheng Yang
A 0.0056-mm2 -249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs. IEEE J. Solid State Circuits 54(1): 88-98 (2019) - [j2]Shiheng Yang, Jun Yin
A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS. IEEE J. Solid State Circuits 54(5): 1351-1362 (2019) - [j1]Ka-Fai Un
A 0.12-mm2 1.2-to-2.4-mW 1.3-to-2.65-GHz Fractional-N Bang-Bang Digital PLL With 8-µs Settling Time for Multi-ISM-Band ULP Radios. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3307-3316 (2019) - [c4]Zunsong Yang
A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur. ISSCC 2019: 270-272 - 2018
- [c3]Shiheng Yang, Jun Yin
A 0.0056mm2 all-digital MDLL using edge re-extraction, dual-ring VCOs and a 0.3mW block-sharing frequency tracking loop achieving 292fsrms Jitter and -249dB FOM. ISSCC 2018: 118-120 - [c2]Jun Yin
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS. ISSCC 2018: 450-452 - 2014
- [c1]Shiheng Yang, Pui-In Mak
A 104μW EMI-resisting bandgap voltage reference achieving -20dB PSRR, and 5% DC shift under a 4dBm EMI level. APCCAS 2014: 57-60
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