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Warren J. Gross
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2020 – today
- 2024
- [j121]Naoya Onizawa
, Ryoma Sasaki, Duckgyu Shin
Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems. IEEE Access 12: 102050-102060 (2024) - [i81]Lulan Shen, Ali Edalati, Brett H. Meyer, Warren J. Gross, James J. Clark:
Robustness to distribution shifts of compressed networks for edge devices. CoRR abs/2401.12014 (2024) - [i80]Lulan Shen, Ali Edalati, Brett H. Meyer, Warren J. Gross, James J. Clark:
AdCorDA: Classifier Refinement via Adversarial Correction and Domain Adaptation. CoRR abs/2401.13212 (2024) - [i79]Mohammadreza Tayaranian, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross:
Faster Inference of Integer SWIN Transformer by Removing the GELU Activation. CoRR abs/2402.01169 (2024) - [i78]Mohammadreza Tayaranian, Seyyed Hasan Mozafari, Brett H. Meyer, James J. Clark, Warren J. Gross:
Automatic Pruning of Fine-tuning Datasets for Transformer-based Language Models. CoRR abs/2407.08887 (2024) - 2023
- [j120]Duckgyu Shin
Memory-Efficient FPGA Implementation of Stochastic Simulated Annealing. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 108-118 (2023) - [j119]Naoya Onizawa
Fast-Converging Simulated Annealing for Ising Models Based on Integral Stochastic Computing. IEEE Trans. Neural Networks Learn. Syst. 34(12): 10999-11005 (2023) - [j118]Syed Mohsin Abbas
List-GRAND: A Practical Way to Achieve Maximum Likelihood Decoding. IEEE Trans. Very Large Scale Integr. Syst. 31(1): 43-54 (2023) - [j117]Huayi Zhou
Low-Complexity Sphere Decoding for Polar-Coded MIMO Systems. IEEE Trans. Veh. Technol. 72(5): 6810-6815 (2023) - [j116]Hung-Yang Chang
PipeBERT: High-throughput BERT Inference for ARM Big.LITTLE Multi-core Processors. J. Signal Process. Syst. 95(7): 877-894 (2023) - [c143]Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer:
Efficient 1D Grouped Convolution for PyTorch a Case Study: Fast On-Device Fine-Tuning for SqueezeBERT. ASAP 2023: 69-75 - [c142]Lulan Shen, Ibtihel Amara, Ruofeng Li, Brett H. Meyer, Warren J. Gross, James J. Clark:
Fast Fine-Tuning Using Curriculum Domain Adaptation. CRV 2023: 296-303 - [c141]Syed Mohsin Abbas
Step-GRAND: A Low Latency Universal Soft-Input Decoder. GLOBECOM (Workshops) 2023: 1668-1673 - [c140]Hung-Yang Chang
High-Throughput Edge Inference for BERT Models via Neural Architecture Search and Pipeline. ACM Great Lakes Symposium on VLSI 2023: 455-459 - [c139]Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer:
Training Acceleration of Frequency Domain CNNs Using Activation Compression. ISCAS 2023: 1-5 - [c138]Huayi Zhou
Hybrid GRAND Sphere Decoding: Accelerated GRAND for Low-Rate Codes. ISCAS 2023: 1-5 - [c137]Marwan Jalaleddine, Huayi Zhou, Jiajie Li, Warren J. Gross:
Partial Ordered Statistics Decoding with Enhanced Error Patterns. ISIT 2023: 1096-1100 - [c136]Ryan Seah, Huayi Zhou, Marwan Jalaleddine, Warren J. Gross:
xSA: A Binary Cross-Entropy Simulated Annealing Polar Decoder. ISTC 2023: 1-5 - [i77]Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu:
Stochastic Quantum Monte Carlo Algorithm for Large-Scale Combinatorial Optimization Problems. CoRR abs/2302.12454 (2023) - [i76]Zhuoran Xiong, Marihan Amein, Olivier Therrien, Warren J. Gross, Brett H. Meyer:
FMAS: Fast Multi-Objective SuperNet Architecture Search for Semantic Segmentation. CoRR abs/2303.16322 (2023) - [i75]Olivier Therrien, Marihan Amein, Zhuoran Xiong, Warren J. Gross, Brett H. Meyer:
SSS3D: Fast Neural Architecture Search For Efficient Three-Dimensional Semantic Segmentation. CoRR abs/2304.11207 (2023) - [i74]Syed Mohsin Abbas, Marwan Jalaleddine, Chi-Ying Tsui, Warren J. Gross:
Step-GRAND: A Low Latency Universal Soft-input Decoder. CoRR abs/2307.07133 (2023) - 2022
- [j115]Nghia Doan
Fast Successive-Cancellation List Flip Decoding of Polar Codes. IEEE Access 10: 5568-5584 (2022) - [j114]Elie Ngomseu Mambou
Improved DC-Free Run-Length Limited 4B6B Codes for Concatenated Schemes. IEEE Access 10: 21847-21852 (2022) - [j113]Jiajie Li
Optimization and Simplification of PCPA Decoder for Reed-Muller Codes. IEEE Commun. Lett. 26(6): 1206-1210 (2022) - [j112]Nghia Doan
Decoding Reed-Muller Codes With Successive Codeword Permutations. IEEE Trans. Commun. 70(11): 7134-7145 (2022) - [j111]Huayi Zhou
A Synchro-Set-Aided Breadth-First Sphere Decoder for Polar-Coded MIMO Systems. IEEE Trans. Signal Process. 70: 6200-6215 (2022) - [j110]Qidie Wu
DsMLP: A Learning-Based Multi-Layer Perception for MIMO Detection Implemented by Dynamic Stochastic Computing. IEEE Trans. Signal Process. 70: 6392-6403 (2022) - [j109]Syed Mohsin Abbas
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND. IEEE Trans. Very Large Scale Integr. Syst. 30(6): 681-693 (2022) - [j108]Nghia Doan
Successive-Cancellation Decoding of Reed-Muller Codes With Fast Hadamard Transform. IEEE Trans. Veh. Technol. 71(11): 11650-11660 (2022) - [j107]Syed Mohsin Abbas
Hardware Architecture for Guessing Random Additive Noise Decoding Markov Order (GRAND-MO). J. Signal Process. Syst. 94(10): 1047-1065 (2022) - [c135]Murray L. Kornelsen, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross:
Fast Heterogeneous Task Mapping for Reducing Edge DNN Latency. ASAP 2022: 64-71 - [c134]Marihan Amein, Zhuoran Xiong, Olivier Therrien, Brett H. Meyer, Warren J. Gross:
Work-in-Progress: SuperNAS: Fast Multi-Objective SuperNet Architecture Search for Semantic Segmentation. CASES 2022: 35-36 - [c133]Negin Firouzian
Work-in-Progress: Utilizing latency and accuracy predictors for efficient hardware-aware NAS. CODES+ISSS 2022: 15-16 - [c132]Lulan Shen, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark:
Conjugate Adder Net (CAddNet) - a Space-Efficient Approximate CNN. CVPR Workshops 2022: 2792-2796 - [c131]Syed Mohsin Abbas
GRAND for Rayleigh Fading Channels. GLOBECOM (Workshops) 2022: 504-509 - [c130]Ibtihel Amara, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark:
CES-KD: Curriculum-based Expert Selection for Guided Knowledge Distillation. ICPR 2022: 1901-1907 - [c129]Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross:
Efficient Fine-Tuning of BERT Models on the Edge. ISCAS 2022: 1838-1842 - [c128]M. Abdelgawad, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross:
BERTPerf: Inference Latency Predictor for BERT on ARM big.LITTLE Multi-Core Processors. SiPS 2022: 1-6 - [i73]Amir Ardakani, Arash Ardakani, Brett H. Meyer, James J. Clark, Warren J. Gross:
Standard Deviation-Based Quantization for Deep Neural Networks. CoRR abs/2202.12422 (2022) - [i72]Syed Mohsin Abbas, Marwan Jalaleddine
GRAND for Rayleigh Fading Channels. CoRR abs/2205.00030 (2022) - [i71]Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross:
Efficient Fine-Tuning of BERT Models on the Edge. CoRR abs/2205.01541 (2022) - [i70]Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross:
Efficient Fine-Tuning of Compressed Language Models with Learners. CoRR abs/2208.02070 (2022) - [i69]Ibtihel Amara, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark:
CES-KD: Curriculum-based Expert Selection for Guided Knowledge Distillation. CoRR abs/2209.07606 (2022) - [i68]Ibtihel Amara, Nazanin Mohammadi Sepahvand, Brett H. Meyer, Warren J. Gross, James J. Clark:
BD-KD: Balancing the Divergences for Online Knowledge Distillation. CoRR abs/2212.12965 (2022) - 2021
- [j106]Amir Ardakani
Training Binarized Neural Networks Using Ternary Multipliers. IEEE Des. Test 38(6): 44-52 (2021) - [j105]Thibaud Tonnellier
On Systematic Polarization-Adjusted Convolutional (PAC) Codes. IEEE Commun. Lett. 25(7): 2128-2132 (2021) - [j104]Huayi Zhou
Low-Complexity Construction of Polar Codes Based on Genetic Algorithm. IEEE Commun. Lett. 25(10): 3175-3179 (2021) - [j103]Warren J. Gross
Hardware-Aware Design for Edge Intelligence. IEEE Open J. Circuits Syst. 2: 113-127 (2021) - [j102]Seyyed Hasan Mozafari
Implementing Convolutional Neural Networks Using Hartley Stochastic Computing With Adaptive Rate Feature Map Compression. IEEE Open J. Circuits Syst. 2: 805-819 (2021) - [j101]Naoya Onizawa
A Design Framework for Invertible Logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 655-665 (2021) - [j100]Nghia Doan
Neural Successive Cancellation Flip Decoding of Polar Codes. J. Signal Process. Syst. 93(6): 631-642 (2021) - [c127]Seyyed Ali Hashemi, Nghia Doan, Warren J. Gross, John M. Cioffi, Andrea Goldsmith:
A Tree Search Approach for Maximum-Likelihood Decoding of Reed-Muller Codes. GLOBECOM (Workshops) 2021: 1-6 - [c126]Thibaud Tonnellier, Marzieh Hashemipour, Nghia Doan, Warren J. Gross, Alexios Balatsoukas-Stimming:
Towards Practical Near-Maximum-Likelihood Decoding of Error-Correcting Codes: An Overview. ICASSP 2021: 8283-8287 - [c125]Syed Mohsin Abbas
High-Throughput VLSI Architecture for Soft-Decision Decoding with ORBGRAND. ICASSP 2021: 8288-8292 - [c124]Nghia Doan, Seyyed Ali Hashemi, Furkan Ercan, Warren J. Gross:
Fast SC-Flip Decoding of Polar Codes with Reinforcement Learning. ICC 2021: 1-6 - [c123]Jiajie Li
Reduced Complexity RPA Decoder for Reed-Muller Codes. ISTC 2021: 1-5 - [c122]Elie Ngomseu Mambou, Thibaud Tonnellier, Warren J. Gross:
Improved Dimming Scheme based on Non-DC Free RLL Codes for VLC. ISTC 2021: 1-5 - [c121]Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer:
Hartley Stochastic Computing For Convolutional Neural Networks. SiPS 2021: 1-6 - [c120]Amir Ardakani, Arash Ardakani, Warren J. Gross:
Fault-Tolerance of Binarized and Stochastic Computing-based Neural Networks. SiPS 2021: 52-57 - [c119]Syed Mohsin Abbas
High-Throughput VLSI Architecture for GRAND Markov Order. SiPS 2021: 158-163 - [i67]Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross:
High-Throughput VLSI architecture for Soft-Decision decoding with ORBGRAND. CoRR abs/2105.07115 (2021) - [i66]Seyyed Ali Hashemi, Nghia Doan, Warren J. Gross, John M. Cioffi, Andrea Goldsmith:
A Tree Search Approach for Maximum-Likelihood Decoding of Reed-Muller Codes. CoRR abs/2107.08991 (2021) - [i65]Nghia Doan, Seyyed Ali Hashemi, Warren J. Gross:
Successive-Cancellation Decoding of Reed-Muller Codes with Fast Hadamard Transform. CoRR abs/2108.12550 (2021) - [i64]Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross:
High-Throughput VLSI Architecture for GRAND Markov Order. CoRR abs/2108.12563 (2021) - [i63]Nghia Doan, Seyyed Ali Hashemi, Marco Mondelli, Warren J. Gross:
Decoding Reed-Muller Codes with Successive Factor-Graph Permutations. CoRR abs/2109.02122 (2021) - [i62]Syed Mohsin Abbas, Marwan Jalaleddine, Warren J. Gross:
List-GRAND: A practical way to achieve Maximum Likelihood Decoding. CoRR abs/2109.12225 (2021) - [i61]Nghia Doan, Seyyed Ali Hashemi, Warren J. Gross:
Fast Successive-Cancellation List Flip Decoding of Polar Codes. CoRR abs/2109.12239 (2021) - [i60]Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Marwan Jalaleddine, Warren J. Gross:
High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND. CoRR abs/2110.13776 (2021) - 2020
- [j99]Duckgyu Shin
Training Hardware for Binarized Convolutional Neural Network Based on CMOS Invertible Logic. IEEE Access 8: 188004-188014 (2020) - [j98]Arash Ardakani
Fast and Efficient Convolutional Accelerator for Edge Computing. IEEE Trans. Computers 69(1): 138-152 (2020) - [j97]Furkan Ercan
Energy-Efficient Hardware Architectures for Fast Polar Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(1): 322-335 (2020) - [j96]Naoya Onizawa
In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 67-I(5): 1541-1550 (2020) - [j95]Zhiwei Zhong
Polar Compiler: Auto-Generator of Hardware Architectures for Polar Encoders. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(6): 2091-2102 (2020) - [j94]Bo Zheng
High-Throughput Low-Latency Encoder and Decoder for a Class of Generalized Reed-Solomon Codes for Short-Reach Optical Communications. IEEE Trans. Circuits Syst. II Express Briefs 67-II(4): 670-674 (2020) - [j93]Furkan Ercan
Practical Dynamic SC-Flip Polar Decoders: Algorithm and Implementation. IEEE Trans. Signal Process. 68: 5441-5456 (2020) - [j92]Huayi Zhou
An Efficient Software Stack Sphere Decoder for Polar Codes. IEEE Trans. Veh. Technol. 69(2): 1257-1266 (2020) - [j91]Huayi Zhou
Efficient Sphere Polar Decoding via Synchronous Determination. IEEE Trans. Veh. Technol. 69(6): 6777-6781 (2020) - [j90]Huayi Zhou, Yuxiang Fu, Zaichen Zhang, Warren J. Gross, Xiaohu You
An Efficient Software List Sphere Decoder for Polar Codes. J. Signal Process. Syst. 92(5): 517-528 (2020) - [j89]Huayi Zhou, Warren J. Gross, Zaichen Zhang, Xiaohu You
A Linear-Complexity Channel-Independent Code Construction Method for List Sphere Polar Decoder. J. Signal Process. Syst. 92(7): 763-774 (2020) - [c118]Zixuan Yin, Warren J. Gross, Brett H. Meyer:
Probabilistic Sequential Multi-Objective Optimization of Convolutional Neural Networks. DATE 2020: 1055-1060 - [c117]Nghia Doan, Seyyed Ali Hashemi, Warren J. Gross:
Decoding Polar Codes with Reinforcement Learning. GLOBECOM 2020: 1-6 - [c116]Furkan Ercan, Thibaud Tonnellier, Nghia Doan, Warren J. Gross:
Simplified Dynamic SC-Flip Polar Decoding. ICASSP 2020: 1733-1737 - [c115]Furkan Ercan, Warren J. Gross:
Fast Thresholded SC-Flip Decoding of Polar Codes. ICC 2020: 1-7 - [c114]Arash Ardakani, Amir Ardakani, Warren J. Gross:
A Regression-Based Method to Synthesize Complex Arithmetic Computations on Stochastic Streams. ISCAS 2020: 1-5 - [c113]Zhengyun Ji, Warren J. Gross:
Towards Efficient On-Chip Learning using Equilibrium Propagation. ISCAS 2020: 1-5 - [c112]Arash Ardakani, Amir Ardakani, Warren J. Gross:
Training Linear Finite-State Machines. NeurIPS 2020 - [c111]Syed Mohsin Abbas
High-Throughput VLSI Architecture for GRAND. SiPS 2020: 1-6 - [i59]Furkan Ercan, Thibaud Tonnellier, Carlo Condo, Warren J. Gross:
Operation Merging for Hardware Implementations of Fast Polar Decoders. CoRR abs/2006.02012 (2020) - [i58]Syed Mohsin Abbas, Thibaud Tonnellier, Furkan Ercan, Warren J. Gross:
High-Throughput VLSI Architecture for GRAND. CoRR abs/2007.07328 (2020) - [i57]Furkan Ercan, Warren J. Gross:
Fast Thresholded SC-Flip Decoding of Polar Codes. CoRR abs/2007.15647 (2020) - [i56]Nghia Doan, Seyyed Ali Hashemi, Warren J. Gross:
Decoding Polar Codes with Reinforcement Learning. CoRR abs/2009.06796 (2020) - [i55]Furkan Ercan, Thibaud Tonnellier, Nghia Doan, Warren J. Gross:
Practical Dynamic SC-Flip Polar Decoders: Algorithm and Implementation. CoRR abs/2009.08547 (2020) - [i54]Thibaud Tonnellier, Warren J. Gross:
On Systematic Polarization-Adjusted Convolutional (PAC) Codes. CoRR abs/2011.03177 (2020)
2010 – 2019
- 2019
- [j88]Carlo Condo
Design and Implementation of a Polar Codes Blind Detection Scheme. IEEE Trans. Circuits Syst. II Express Briefs 66-II(6): 943-947 (2019) - [j87]Sean C. Smithson
Efficient CMOS Invertible Logic Using Stochastic Computing. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2263-2274 (2019) - [j86]Furkan Ercan
Improved Bit-Flipping Algorithm for Successive Cancellation Decoding of Polar Codes. IEEE Trans. Commun. 67(1): 61-72 (2019) - [j85]Kaining Han
Stochastic Bit-Wise Iterative Decoding of Polar Codes. IEEE Trans. Signal Process. 67(5): 1138-1151 (2019) - [j84]Seyyed Ali Hashemi
Rate-Flexible Fast Polar Decoders. IEEE Trans. Signal Process. 67(22): 5689-5701 (2019) - [j83]Huayi Zhou
An Improved Software List Sphere Polar Decoder With Synchronous Determination. IEEE Trans. Veh. Technol. 68(6): 5236-5245 (2019) - [j82]Furkan Ercan
Operation Merging for Hardware Implementations of Fast Polar Decoders. J. Signal Process. Syst. 91(9): 995-1007 (2019) - [c110]Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
A Design Framework for Invertible Logic. ACSSC 2019: 312-316 - [c109]Seyyed Ali Hashemi
Deep-Learning-Aided Successive-Cancellation Decoding of Polar Codes. ACSSC 2019: 532-536 - [c108]Thibaud Tonnellier
Length-Compatible Polar Codes: A Survey : (Invited Paper). CISS 2019: 1-6 - [c107]Arash Ardakani, Zhengyun Ji, Warren J. Gross:
Learning to Skip Ineffectual Recurrent Computations in LSTMs. DATE 2019: 1427-1432 - [c106]Elie Ngomseu Mambou, Thibaud Tonnellier, Seyyed Ali Hashemi, Warren J. Gross:
Efficient Flicker-Free FEC Codes Using Knuth's Balancing Algorithm for VLC. GLOBECOM 2019: 1-6 - [c105]Adam Cavatassi, Thibaud Tonnellier
Asymmetric Construction of Low-Latency and Length-Flexible Polar Codes. ICC 2019: 1-6 - [c104]Nghia Doan, Seyyed Ali Hashemi
Neural Belief Propagation Decoding of CRC-Polar Concatenated Codes. ICC 2019: 1-6 - [c103]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
Stochastic-Computing Based Brainwave LSI Towards an Intelligence Edge. ICECS 2019: 434-437 - [c102]Arash Ardakani, Zhengyun Ji, Sean C. Smithson, Brett H. Meyer, Warren J. Gross:
Learning Recurrent Binary/Ternary Weights. ICLR (Poster) 2019 - [c101]Seyyed Ali Hashemi
Rate-Flexible Fast Polar Decoders. ITW 2019: 1-5 - [c100]Arash Ardakani, Zhengyun Ji, Amir Ardakani, Warren J. Gross:
The Synthesis of XNOR Recurrent Neural Networks with Stochastic Logic. NeurIPS 2019: 8442-8452 - [c99]Nghia Doan, Seyyed Ali Hashemi
Neural Dynamic Successive Cancellation Flip Decoding of Polar Codes. SiPS 2019: 272-277 - [c98]Adam Cavatassi, Thibaud Tonnellier, Warren J. Gross:
Fast Decoding of Multi-Kernel Polar Codes. WCNC 2019: 1-6 - [i53]Adam Cavatassi, Thibaud Tonnellier, Warren J. Gross:
Fast Decoding of Multi-Kernel Polar Codes. CoRR abs/1902.01922 (2019) - [i52]Adam Cavatassi, Thibaud Tonnellier, Warren J. Gross:
Asymmetric Construction of Low-Latency and Length-Flexible Polar Codes. CoRR abs/1902.02402 (2019) - [i51]Seyyed Ali Hashemi, Carlo Condo, Marco Mondelli, Warren J. Gross:
Rate-Flexible Fast Polar Decoders. CoRR abs/1903.09203 (2019) - [i50]Nghia Doan, Seyyed Ali Hashemi, Furkan Ercan, Thibaud Tonnellier, Warren J. Gross:
Neural Dynamic Successive Cancellation Flip Decoding of Polar Codes. CoRR abs/1907.11563 (2019) - [i49]Elie Ngomseu Mambou, Thibaud Tonnellier, Seyyed Ali Hashemi, Warren J. Gross:
Efficient Flicker-Free FEC Codes using Knuth's Balancing Algorithm for VLC. CoRR abs/1908.05798 (2019) - [i48]Seyyed Ali Hashemi, Nghia Doan, Thibaud Tonnellier, Warren J. Gross:
Deep-Learning-Aided Successive-Cancellation Decoding of Polar Codes. CoRR abs/1912.01086 (2019) - 2018
- [j81]Naoya Onizawa
An Accuracy/Energy-Flexible Configurable Gabor-Filter Chip Based on Stochastic Computation With Dynamic Voltage-Frequency-Length Scaling. IEEE J. Emerg. Sel. Topics Circuits Syst. 8(3): 444-453 (2018) - [j80]Eliya Nachmani
Deep Learning Methods for Improved Decoding of Linear Codes. IEEE J. Sel. Top. Signal Process. 12(1): 119-131 (2018) - [j79]Arash Ardakani
An Architecture to Accelerate Convolution in Deep Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(4): 1349-1362 (2018) - [j78]Carlo Condo
A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(4): 1420-1431 (2018) - [j77]Gabriele Coppolino
A Multi-Kernel Multi-Code Polar Decoder Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(12): 4413-4422 (2018) - [j76]François Leduc-Primeau
Modeling and Energy Optimization of LDPC Decoder Circuits With Timing Violations. IEEE Trans. Commun. 66(3): 932-946 (2018) - [j75]Seyyed Ali Hashemi
Decoder Partitioning: Towards Practical List Decoding of Polar Codes. IEEE Trans. Commun. 66(9): 3749-3759 (2018) - [j74]Hayden Kwok-Hay So
Introduction to the Special Issue on Application-Specific Systems, Architectures and Processors. J. Signal Process. Syst. 90(1): 1-2 (2018) - [j73]Andrew J. Wong, Saied Hemati, Warren J. Gross:
A Modular Architecture for Structured Long Block-Length LDPC Decoders. J. Signal Process. Syst. 90(1): 29-38 (2018) - [j72]Pascal Giard
Fast Low-Complexity Decoders for Low-Rate Polar Codes. J. Signal Process. Syst. 90(5): 675-685 (2018) - [j71]Kaushik Boga
A Generalized Stochastic Implementation of the Disparity Energy Model for Depth Perception. J. Signal Process. Syst. 90(5): 709-725 (2018) - [j70]Pascal Giard, Gabi Sarkis, Camille Leroux, Claude Thibeault, Warren J. Gross:
Low-Latency Software Polar Decoders. J. Signal Process. Syst. 90(5): 761-775 (2018) - [c97]Loren Lugosch, Warren J. Gross:
Learning from the Syndrome. ACSSC 2018: 594-598 - [c96]Nghia Doan, Seyyed Ali Hashemi
On the Decoding of Polar Codes on Permuted Factor Graphs. GLOBECOM 2018: 1-6 - [c95]Kaining Han, Junchao Wang, Warren J. Gross:
Bit-Wise Iterative Decoding of Polar Codes using Stochastic Computing. ACM Great Lakes Symposium on VLSI 2018: 409-414 - [c94]Furkan Ercan
Partitioned Successive-Cancellation Flip Decoding of Polar Codes. ICC 2018: 1-6 - [c93]Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu:
Study of Stochastic Invertible Multiplier Designs. ICECS 2018: 649-650 - [c92]Arash Ardakani, Carlo Condo, Warren J. Gross:
A Convolutional Accelerator for Neural Networks With Binary Weights. ISCAS 2018: 1-5 - [c91]Harsh Aurora, Carlo Condo, Warren J. Gross:
Low-Complexity Software Stack Decoding of Polar Codes. ISCAS 2018: 1-5 - [c90]Seyyed Ali Hashemi
Decoding Reed-Muller and Polar Codes by Successive Factor Graph Permutations. ISTC 2018: 1-5 - [c89]Kaining Han, Junchao Wang, Warren J. Gross:
Stochastic Computing based BCH Decoder for WBAN Systems. MWSCAS 2018: 729-732 - [c88]Mehdi Ahmadi, Shervin Vakili
Power Reduction in CNN Pooling Layers with a Preliminary Partial Computation Strategy. NEWCAS 2018: 125-129 - [c87]Arash Ardakani, Carlo Condo, Warren J. Gross:
A Multi-Mode Accelerator for Pruned Deep Neural Networks. NEWCAS 2018: 352-355 - [c86]Gabriele Coppolino, Carlo Condo, Guido Masera, Warren J. Gross:
Efficient Operation Scheduling in Successive-Cancellation-based polar decoders. SiPS 2018: 83-87 - [c85]Nghia Doan, Seyyed Ali Hashemi
Neural Successive Cancellation Decoding of Polar Codes. SPAWC 2018: 1-5 - [c84]Carlo Condo, Furkan Ercan
Improved successive cancellation flip decoding of polar codes based on error distribution. WCNC Workshops 2018: 19-24 - [i47]Carlo Condo, Seyyed Ali Hashemi, Arash Ardakani, Furkan Ercan, Warren J. Gross:
Design and Implementation of a Polar Codes Blind Detection Scheme. CoRR abs/1801.01820 (2018) - [i46]Gabriele Coppolino, Carlo Condo, Guido Masera, Warren J. Gross:
A Multi-Kernel Multi-Code Polar Decoder Architecture. CoRR abs/1802.00580 (2018) - [i45]Nghia Doan, Seyyed Ali Hashemi, Marco Mondelli, Warren J. Gross:
On the Decoding of Polar Codes on Permuted Factor Graphs. CoRR abs/1806.11195 (2018) - [i44]Seyyed Ali Hashemi, Nghia Doan, Marco Mondelli, Warren J. Gross:
Decoding Reed-Muller and Polar Codes by Successive Factor Graph Permutations. CoRR abs/1807.03912 (2018) - [i43]Furkan Ercan, Carlo Condo, Warren J. Gross:
Improved Bit-Flipping Algorithm for Successive Cancellation Decoding of Polar Codes. CoRR abs/1808.03616 (2018) - [i42]Harsh Aurora, Warren J. Gross:
Towards Practical Software Stack Decoding of Polar Codes. CoRR abs/1809.03606 (2018) - [i41]Arash Ardakani, Zhengyun Ji, Sean C. Smithson, Brett H. Meyer, Warren J. Gross:
Learning Recurrent Binary/Ternary Weights. CoRR abs/1809.11086 (2018) - [i40]Loren Lugosch, Warren J. Gross:
Learning from the Syndrome. CoRR abs/1810.10902 (2018) - [i39]Nghia Doan, Seyyed Ali Hashemi, Elie Ngomseu Mambou, Thibaud Tonnellier, Warren J. Gross:
Neural Belief Propagation Decoding of CRC-Polar Concatenated Codes. CoRR abs/1811.00124 (2018) - [i38]Arash Ardakani, Zhengyun Ji, Warren J. Gross:
Learning to Skip Ineffectual Recurrent Computations in LSTMs. CoRR abs/1811.10396 (2018) - 2017
- [b1]Pascal Giard, Claude Thibeault, Warren J. Gross:
High-Speed Decoders for Polar Codes. Springer 2017, ISBN 978-3-319-59781-2, pp. 1-98 - [j69]Seyyed Ali Hashemi
Memory-Efficient Polar Decoders. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(4): 604-615 (2017) - [j68]Pascal Giard
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. IEEE J. Emerg. Sel. Topics Circuits Syst. 7(4): 616-629 (2017) - [j67]Carlo Condo
Blind Detection With Polar Codes. IEEE Commun. Lett. 21(12): 2550-2553 (2017) - [j66]Carlo Condo
Implementation of Sparse Superposition Codes. IEEE Trans. Signal Process. 65(9): 2421-2427 (2017) - [j65]Seyyed Ali Hashemi
Fast and Flexible Successive-Cancellation List Decoders for Polar Codes. IEEE Trans. Signal Process. 65(21): 5756-5769 (2017) - [j64]Arash Ardakani
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2688-2699 (2017) - [c83]Seyyed Ali Hashemi
On the performance of polar codes for 5G eMBB control channel. ACSSC 2017: 1764-1768 - [c82]Furkan Ercan
On error-correction performance and implementation of polar code list decoders for 5G. Allerton 2017: 443-449 - [c81]Naoya Onizawa, Kazumichi Matsumiya
Accuracy/energy-flexible stochastic configurable 2D Gabor filter with instant-on capability. ESSCIRC 2017: 43-46 - [c80]François D. Côté, Ioannis N. Psaromiligkos, Warren J. Gross:
A theory of generalized proximity for ADMM. GlobalSIP 2017: 578-582 - [c79]Arash Ardakani, Carlo Condo, Warren J. Gross:
Activation pruning of deep convolutional neural networks. GlobalSIP 2017: 1325-1329 - [c78]Seyyed Ali Hashemi
Partitioned List Decoding of Polar Codes: Analysis and Improvement of Finite Length Performance. GLOBECOM 2017: 1-7 - [c77]François D. Côté, Ioannis N. Psaromiligkos, Warren J. Gross:
A distributed constrained-form support vector machine. ICASSP 2017: 4242-4246 - [c76]Arash Ardakani, Carlo Condo, Warren J. Gross:
Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks. ICLR (Poster) 2017 - [c75]Loren Lugosch, Warren J. Gross:
Neural offset min-sum decoding. ISIT 2017: 1361-1365 - [c74]Carlo Condo, Seyyed Ali Hashemi
Efficient bit-channel reliability computation for multi-mode polar code encoders and decoders. SiPS 2017: 1-6 - [c73]Furkan Ercan
Reduced-memory high-throughput fast-SSC polar code decoder architecture. SiPS 2017: 1-6 - [c72]Seyyed Ali Hashemi
Fast Simplified Successive-Cancellation List Decoding of Polar Codes. WCNC Workshops 2017: 1-6 - [i37]Loren Lugosch, Warren J. Gross:
Neural Offset Min-Sum Decoding. CoRR abs/1701.05931 (2017) - [i36]Seyyed Ali Hashemi, Carlo Condo, Warren J. Gross:
Fast Simplified Successive-Cancellation List Decoding of Polar Codes. CoRR abs/1701.08126 (2017) - [i35]Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andreas Peter Burg, Claude Thibeault, Warren J. Gross:
A Multi-Gbps Unrolled Hardware List Decoder for a Systematic Polar Code. CoRR abs/1702.00938 (2017) - [i34]Seyyed Ali Hashemi, Carlo Condo, Warren J. Gross:
Fast and Flexible Successive-Cancellation List Decoders for Polar Codes. CoRR abs/1703.08208 (2017) - [i33]Carlo Condo, Seyyed Ali Hashemi, Warren J. Gross:
Blind Detection with Polar Codes. CoRR abs/1705.01864 (2017) - [i32]Seyyed Ali Hashemi, Marco Mondelli, S. Hamed Hassani, Rüdiger L. Urbanke, Warren J. Gross:
Partitioned List Decoding of Polar Codes: Analysis and Improvement of Finite Length Performance. CoRR abs/1705.05497 (2017) - [i31]Carlo Condo, Seyyed Ali Hashemi, Warren J. Gross:
Efficient Bit-Channel Reliability Computation for Multi-Mode Polar Code Encoders and Decoders. CoRR abs/1705.05674 (2017) - [i30]Eliya Nachmani, Elad Marciano, Loren Lugosch, Warren J. Gross, David Burshtein, Yair Be'ery:
Deep Learning Methods for Improved Decoding of Linear Codes. CoRR abs/1706.07043 (2017) - [i29]Furkan Ercan, Carlo Condo, Seyyed Ali Hashemi, Warren J. Gross:
On Error-Correction Performance and Implementation of Polar Code List Decoders for 5G. CoRR abs/1708.04706 (2017) - [i28]Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andrea Bonetti, Claude Thibeault, Warren J. Gross, Philippe Flatresse, Andreas Burg:
PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. CoRR abs/1708.09603 (2017) - [i27]Furkan Ercan, Carlo Condo, Seyyed Ali Hashemi, Warren J. Gross:
Partitioned Successive-Cancellation Flip Decoding of Polar Codes. CoRR abs/1711.11093 (2017) - [i26]Carlo Condo, Furkan Ercan, Warren J. Gross:
Improved Successive Cancellation Flip Decoding of Polar Codes Based on Error Distribution. CoRR abs/1711.11096 (2017) - [i25]Arash Ardakani, Carlo Condo, Warren J. Gross:
Multi-Mode Inference Engine for Convolutional Neural Networks. CoRR abs/1712.03994 (2017) - 2016
- [j63]Naoya Onizawa, Hooman Jarollahi, Takahiro Hanyu, Warren J. Gross:
Hardware Implementation of Associative Memories Based on Multiple-Valued Sparse Clustered Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 6(1): 13-24 (2016) - [j62]Saied Hemati, François Leduc-Primeau, Warren J. Gross:
A Relaxed Min-Sum LDPC Decoder With Simplified Check Nodes. IEEE Commun. Lett. 20(3): 422-425 (2016) - [j61]Gabi Sarkis, Pascal Giard, Alexander Vardy
Fast List Decoders for Polar Codes. IEEE J. Sel. Areas Commun. 34(2): 318-328 (2016) - [j60]Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross:
Multi-Mode Unrolled Architectures for Polar Decoders. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(9): 1443-1453 (2016) - [j59]Seyyed Ali Hashemi
A Fast Polar Code List Decoder Architecture Based on Sphere Decoding. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(12): 2368-2380 (2016) - [j58]Gabi Sarkis, Ido Tal, Pascal Giard, Alexander Vardy
Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes. IEEE Trans. Commun. 64(7): 2732-2745 (2016) - [j57]François Leduc-Primeau, Vincent Gripon, Michael G. Rabbat, Warren J. Gross:
Fault-Tolerant Associative Memories Based on c-Partite Graphs. IEEE Trans. Signal Process. 64(4): 829-841 (2016) - [j56]Warren J. Gross, Zhiyuan Yan:
Guest Editorial: Design and Implementation of DSP Systems. J. Signal Process. Syst. 85(1): 1-3 (2016) - [c71]Pascal Giard, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Andreas Peter Burg
A multi-Gbps unrolled hardware list decoder for a systematic polar code. ACSSC 2016: 1194-1198 - [c70]Mehdi Ahmadi, Warren J. Gross, Samuel Kadoury:
A real-time remote video streaming platform for ultrasound imaging. EMBC 2016: 4383-4386 - [c69]François D. Côté, Ioannis N. Psaromiligkos, Warren J. Gross:
In-network linear regression with arbitrarily split data matrices. GlobalSIP 2016: 580-584 - [c68]Carlo Condo, François Leduc-Primeau, Gabi Sarkis, Pascal Giard, Warren J. Gross:
Stall pattern avoidance in polynomial product codes. GlobalSIP 2016: 699-702 - [c67]Seyyed Ali Hashemi
Partitioned successive-cancellation list decoding of polar codes. ICASSP 2016: 957-960 - [c66]Arash Ardakani, François Leduc-Primeau, Warren J. Gross:
Hardware implementation of FIR/IIR digital filters using integral stochastic computation. ICASSP 2016: 6540-6544 - [c65]Sean C. Smithson, Guang Yang, Warren J. Gross, Brett H. Meyer:
Neural networks designing neural networks: multi-objective hyper-parameter optimization. ICCAD 2016: 104 - [c64]Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui
Hardware decoders for polar codes: An overview. ISCAS 2016: 149-152 - [c63]Seyyed Ali Hashemi
Matrix reordering for efficient list sphere decoding of polar codes. ISCAS 2016: 1730-1733 - [c62]Seyyed Ali Hashemi
Simplified Successive-Cancellation List decoding of polar codes. ISIT 2016: 815-819 - [c61]Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
VLSI implementation of deep neural networks using integral stochastic computing. ISTC 2016: 216-220 - [c60]François Leduc-Primeau, Warren J. Gross:
Finite-length quasi-synchronous LDPC decoders. ISTC 2016: 325-329 - [c59]Scott Dickson Dagondon, Warren J. Gross, Brett H. Meyer:
Sparse-Clustered Network with Selective Decoding for Internet Traffic Classification. SiPS 2016: 177-182 - [c58]Sean C. Smithson, Kaushik Boga, Arash Ardakani, Brett H. Meyer, Warren J. Gross:
Stochastic Computing Can Improve Upon Digital Spiking Neural Networks. SiPS 2016: 309-314 - [i24]Pascal Giard, Alexios Balatsoukas-Stimming, Gabi Sarkis, Claude Thibeault, Warren J. Gross:
Fast Low-Complexity Decoders for Low-Rate Polar Codes. CoRR abs/1603.05273 (2016) - [i23]Pascal Giard, Gabi Sarkis, Alexios Balatsoukas-Stimming, YouZhe Fan, Chi-Ying Tsui, Andreas Burg, Claude Thibeault, Warren J. Gross:
Hardware Decoders for Polar Codes: An Overview. CoRR abs/1606.00737 (2016) - [i22]Carlo Condo, Pascal Giard, François Leduc-Primeau, Gabi Sarkis, Warren J. Gross:
A 9.96 dB NCG FEC scheme and 164 bits/cycle low-complexity product decoder architecture. CoRR abs/1610.06050 (2016) - [i21]Arash Ardakani, Carlo Condo, Warren J. Gross:
Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks. CoRR abs/1611.01427 (2016) - [i20]Sean C. Smithson, Guang Yang, Warren J. Gross, Brett H. Meyer:
Neural Networks Designing Neural Networks: Multi-Objective Hyper-Parameter Optimization. CoRR abs/1611.02120 (2016) - [i19]Carlo Condo, François Leduc-Primeau, Gabi Sarkis, Pascal Giard, Warren J. Gross:
Stall Pattern Avoidance in Polynomial Product Codes. CoRR abs/1611.04834 (2016) - 2015
- [j55]Yousef El-Kurdi
Parallel finite element technique using Gaussian belief propagation. Comput. Phys. Commun. 193: 38-48 (2015) - [j54]Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya
Gabor Filter Based on Stochastic Computation. IEEE Signal Process. Lett. 22(9): 1224-1228 (2015) - [j53]Bojan Mihajlovic, Zeljko Zilic, Warren J. Gross:
Architecture-Aware Real-Time Compression of Execution Traces. ACM Trans. Embed. Comput. Syst. 14(4): 75:1-75:24 (2015) - [j52]Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross:
Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 642-653 (2015) - [c57]Seyyed Ali Hashemi
List sphere decoding of polar codes. ACSSC 2015: 1346-1350 - [c56]Glenn E. R. Cowan, Kevin Cushon
Mixed-signal implementation of differential decoding using binary message passing algorithms. ASAP 2015: 116-119 - [c55]Andrew J. Wong, Saied Hemati, Warren J. Gross:
Efficient implementation of structured long block-length LDPC codes. ASAP 2015: 234-238 - [c54]Robin Danilo, Philippe Coussy, Laura Conde-Canencia, Vincent Gripon, Warren J. Gross:
Restricted Clustered Neural Network for Storing Real Data. ACM Great Lakes Symposium on VLSI 2015: 205-210 - [c53]François Leduc-Primeau, Frank R. Kschischang
Energy optimization of LDPC decoder circuits with timing violations. ICC 2015: 412-417 - [c52]Naoya Onizawa, Daisaku Katagiri, Kazumichi Matsumiya
Frequency-flexible stochastic Gabor filter. DSP 2015: 458-462 - [c51]Robin Danilo, Hooman Jarollahi, Vincent Gripon, Philippe Coussy, Laura Conde-Canencia, Warren J. Gross:
Algorithm and implementation of an associative memory for oriented edge detection using improved clustered neural networks. ISCAS 2015: 2501-2504 - [c50]Kaushik Boga, Naoya Onizawa, François Leduc-Primeau, Kazumichi Matsumiya
Stochastic implementation of the disparity energy model for depth perception. SiPS 2015: 1-6 - [c49]Carlo Condo, Warren J. Gross:
Sparse superposition codes: A practical approach. SiPS 2015: 1-6 - [c48]Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross:
A 638 Mbps low-complexity rate 1/2 polar decoder on FPGAs. SiPS 2015: 1-6 - [i18]François Leduc-Primeau, Frank R. Kschischang, Warren J. Gross:
Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations. CoRR abs/1503.03880 (2015) - [i17]Pascal Giard, Gabi Sarkis, Camille Leroux, Claude Thibeault, Warren J. Gross:
Low-Latency Software Polar Decoders. CoRR abs/1504.00353 (2015) - [i16]Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross:
Unrolled Polar Decoders, Part I: Hardware Architectures. CoRR abs/1505.01459 (2015) - [i15]Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross:
Unrolled Polar Decoders, Part II: Fast List Decoders. CoRR abs/1505.01466 (2015) - [i14]Gabi Sarkis, Ido Tal, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross:
Flexible and Low-Complexity Encoding and Decoding of Systematic Polar Codes. CoRR abs/1507.03614 (2015) - [i13]Arash Ardakani, François Leduc-Primeau, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
VLSI Implementation of Deep Neural Network Using Integral Stochastic Computing. CoRR abs/1509.08972 (2015) - [i12]Seyyed Ali Hashemi, Alexios Balatsoukas-Stimming, Pascal Giard, Claude Thibeault, Warren J. Gross:
Partitioned Successive-Cancellation List Decoding of Polar Codes. CoRR abs/1512.03128 (2015) - 2014
- [j51]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross:
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture. IEEE J. Emerg. Sel. Topics Circuits Syst. 4(4): 460-474 (2014) - [j50]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
Asynchronous Stochastic Decoding of LDPC Codes: Algorithm and Simulation Model. IEICE Trans. Inf. Syst. 97-D(9): 2286-2295 (2014) - [j49]François D. Côté, Ioannis N. Psaromiligkos, Warren J. Gross:
On the Chandra-Poram-Bose symbol error probability expression for coherent orthogonal M-ary frequency shift keying. Int. J. Commun. Syst. 27(10): 2092-2096 (2014) - [j48]Gabi Sarkis, Pascal Giard, Alexander Vardy
Fast Polar Decoders: Algorithm and Implementation. IEEE J. Sel. Areas Commun. 32(5): 946-957 (2014) - [j47]Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(3): 865-876 (2014) - [j46]Alexios Balatsoukas-Stimming, Alexandre J. Raymond, Warren J. Gross, Andreas Burg
Hardware Architecture for List Successive Cancellation Decoding of Polar Codes. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 609-613 (2014) - [j45]Bojan Mihajlovic, Zeljko Zilic, Warren J. Gross:
Dynamically Instrumenting the QEMU Emulator for Linux Process Trace Generation with the GDB Debugger. ACM Trans. Embed. Comput. Syst. 13(5s): 167:1-167:18 (2014) - [j44]Kevin Cushon
High-Throughput Energy-Efficient LDPC Decoders Using Differential Binary Message Passing. IEEE Trans. Signal Process. 62(3): 619-631 (2014) - [j43]Alexandre J. Raymond, Warren J. Gross:
A Scalable Successive-Cancellation Decoder for Polar Codes. IEEE Trans. Signal Process. 62(20): 5339-5347 (2014) - [j42]Warren J. Gross, Naveen Verma, Tong Zhang:
Recent Advances in Design and Implementation of Signal Processing Systems. J. Signal Process. Syst. 76(2): 91-93 (2014) - [j41]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
Clockless Stochastic Decoding of Low-Density Parity-Check Codes: Architecture and Simulation Model. J. Signal Process. Syst. 76(2): 185-194 (2014) - [j40]Warren J. Gross, Zhiyuan Yan:
Latest Advances on Design and Implementation of DSP Systems. J. Signal Process. Syst. 76(3): 223-224 (2014) - [j39]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross:
Algorithm and Architecture of Fully-Parallel Associative Memories Based on Sparse Clustered Networks. J. Signal Process. Syst. 76(3): 235-247 (2014) - [c47]Kevin Cushon
Energy-efficient gear-shift LDPC decoders. ASAP 2014: 219-223 - [c46]Gabi Sarkis, Pascal Giard, Claude Thibeault, Warren J. Gross:
Autogenerating software polar decoders. GlobalSIP 2014: 6-10 - [c45]Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross:
Fast software polar decoders. ICASSP 2014: 7555-7559 - [c44]François Leduc-Primeau, Vincent Gripon, Michael G. Rabbat, Warren J. Gross:
Cluster-based associative memories built from unreliable storage. ICASSP 2014: 8370-8374 - [c43]Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
Associative Memories Based on Multiple-Valued Sparse Clustered Networks. ISMVL 2014: 208-213 - [c42]Naoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu:
Analog-to-stochastic converter using magnetic-tunnel junction devices. NANOARCH 2014: 59-64 - [c41]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Takahiro Hanyu, Warren J. Gross:
Algorithm and architecture for a multiple-field context-driven search engine using fully-parallel clustered associative memories. SiPS 2014: 133-138 - [c40]Gabi Sarkis, Pascal Giard, Alexander Vardy
Increasing the speed of polar list decoders. SiPS 2014: 215-220 - [i11]Hooman Jarollahi, Naoya Onizawa, Takahiro Hanyu, Warren J. Gross:
Associative Memories Based on Multiple-Valued Sparse Clustered Networks. CoRR abs/1402.0808 (2014) - [i10]Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross:
Increasing the Speed of Polar List Decoders. CoRR abs/1407.2921 (2014) - [i9]Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross:
A 237 Gbps Unrolled Hardware Polar Decoder. CoRR abs/1412.6043 (2014) - 2013
- [j38]Gabi Sarkis, Warren J. Gross:
Increasing the Throughput of Polar Decoders. IEEE Commun. Lett. 17(4): 725-728 (2013) - [j37]Naoya Onizawa, Shoun Matsunaga, Vincent C. Gaudet
High-throughput CAM based on a synchronous overlapped search scheme. IEICE Electron. Express 10(7): 20130148 (2013) - [j36]Gabi Sarkis, Saied Hemati, Shie Mannor
Stochastic Decoding of LDPC Codes over GF(q). IEEE Trans. Commun. 61(3): 939-950 (2013) - [j35]François Leduc-Primeau, Saied Hemati, Shie Mannor
Relaxed Half-Stochastic Belief Propagation. IEEE Trans. Commun. 61(5): 1648-1659 (2013) - [j34]Camille Leroux, Alexandre J. Raymond, Gabi Sarkis, Warren J. Gross:
A Semi-Parallel Successive-Cancellation Decoder for Polar Codes. IEEE Trans. Signal Process. 61(2): 289-299 (2013) - [j33]Alexandru Ciobanu, Saied Hemati, Warren J. Gross:
Adaptive Multiset Stochastic Decoding of Non-Binary LDPC Codes. IEEE Trans. Signal Process. 61(16): 4100-4113 (2013) - [j32]Jarmo Takala
Guest Editors' Introduction to Special Issue on Advances in DSP System Design. J. Signal Process. Syst. 71(3): 169-171 (2013) - [c39]Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross:
A low-power Content-Addressable Memory based on clustered-sparse networks. ASAP 2013: 305-308 - [c38]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu:
A Low-Energy Variation-Tolerant Asynchronous TCAM for Network Intrusion Detection Systems. ASYNC 2013: 8-15 - [c37]Naoya Onizawa, Warren J. Gross:
Low-power area-efficient large-scale IP lookup engine based on binary-weighted clustered networks. DAC 2013: 55:1-55:6 - [c36]Hooman Jarollahi, Naoya Onizawa, Warren J. Gross:
Selective decoding in associative memories based on Sparse-Clustered Networks. GlobalSIP 2013: 1270-1273 - [c35]Alexandre J. Raymond, Warren J. Gross:
Scalable successive-cancellation hardware decoder for polar codes. GlobalSIP 2013: 1282-1285 - [c34]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross:
Reduced-complexity binary-weight-coded associative memories. ICASSP 2013: 2523-2527 - [c33]Gabi Sarkis, Warren J. Gross:
Polar codes for data storage applications. ICNC 2013: 840-844 - [c32]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
Lowering Error Floors in Stochastic Decoding of LDPC Codes Based on Wire-Delay Dependent Asynchronous Updating. ISMVL 2013: 254-259 - [i8]Hooman Jarollahi, Vincent Gripon, Naoya Onizawa, Warren J. Gross:
A Low-Power Content-Addressable-Memory Based on Clustered-Sparse-Networks. CoRR abs/1302.4463 (2013) - [i7]Alexandre J. Raymond, Warren J. Gross:
Scalable Successive-Cancellation Hardware Decoder for Polar Codes. CoRR abs/1306.3529 (2013) - [i6]Pascal Giard, Gabi Sarkis, Claude Thibeault, Warren J. Gross:
A Fast Software Polar Decoder. CoRR abs/1306.6311 (2013) - [i5]Gabi Sarkis, Pascal Giard, Alexander Vardy, Claude Thibeault, Warren J. Gross:
Fast Polar Decoders: Algorithm and Implementation. CoRR abs/1307.7154 (2013) - [i4]Hooman Jarollahi, Naoya Onizawa, Warren J. Gross:
Selective Decoding in Associative Memories Based on Sparse-Clustered Networks. CoRR abs/1308.6021 (2013) - 2012
- [j31]Gabi Sarkis, Warren J. Gross:
Efficient Stochastic Decoding of Non-Binary LDPC Codes with Degree-Two Variable Nodes. IEEE Commun. Lett. 16(3): 389-391 (2012) - [j30]Guanghua He, Gabi Sarkis, Saied Hemati, Warren J. Gross, Baoming Bai:
Low-Complexity Channel-Likelihood Estimation for Non-Binary Codes and QAM. IEEE Commun. Lett. 16(6): 801-804 (2012) - [j29]François Leduc-Primeau, Saied Hemati, Shie Mannor
Dithered Belief Propagation Decoding. IEEE Trans. Commun. 60(8): 2042-2047 (2012) - [j28]Camille Leroux, Alexandre J. Raymond, Gabi Sarkis, Ido Tal, Alexander Vardy
Hardware Implementation of Successive-Cancellation Decoders for Polar Codes. J. Signal Process. Syst. 69(3): 305-315 (2012) - [c31]François Leduc-Primeau, Warren J. Gross:
Faulty Gallager-B decoding with optimal message repetition. Allerton Conference 2012: 549-556 - [c30]François Leduc-Primeau, Alexandre J. Raymond, Pascal Giard, Kevin Cushon, Claude Thibeault, Warren J. Gross:
High-throughput LDPC decoding using the RHS algorithm. DASIP 2012: 1-6 - [c29]Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Warren J. Gross:
Architecture and implementation of an associative memory using sparse clustered networks. ISCAS 2012: 2901-2904 - [c28]Yousef El-Kurdi, Dennis Giannacopoulos, Warren J. Gross:
Relaxed Gaussian Belief Propagation. ISIT 2012: 2002-2006 - [c27]Naoya Onizawa, Vincent C. Gaudet
Asynchronous Stochastic Decoding of Low-Density Parity-Check Codes. ISMVL 2012: 92-97 - [c26]Vincent Gripon, Vitaly Skachek, Warren J. Gross, Michael G. Rabbat:
Random clique codes. ISTC 2012: 121-125 - [c25]Vincent Gripon, Michael G. Rabbat, Vitaly Skachek, Warren J. Gross:
Compressing multisets using tries. ITW 2012: 642-646 - [c24]Romain Heloir, Camille Leroux, Saied Hemati, Matthieu Arzel, Warren J. Gross:
Stochastic chase decoder for reed-solomon codes. NEWCAS 2012: 5-8 - [c23]Saeed Sharifi Tehrani, Paul H. Siegel, Shie Mannor
Joint Stochastic Decoding of LDPC Codes and Partial-Response Channels. SiPS 2012: 13-18 - [c22]Naoya Onizawa, Warren J. Gross, Takahiro Hanyu, Vincent C. Gaudet
Clockless Stochastic Decoding of Low-Density Parity-Check Codes. SiPS 2012: 143-148 - [i3]François Leduc-Primeau, Saied Hemati, Shie Mannor, Warren J. Gross:
Relaxed Half-Stochastic Belief Propagation. CoRR abs/1205.2428 (2012) - 2011
- [j27]Meer N. Sakib, V. Mahalingam, Warren J. Gross, Odile Liboiron-Ladouceur
Optical Front-End for Soft-Decision LDPC Codes in Optical Communication Systems. JOCN 3(6): 533-541 (2011) - [j26]François D. Côté, Ioannis N. Psaromiligkos, Warren J. Gross:
GNSS Modulation: A Unified Statistical Description. IEEE Trans. Aerosp. Electron. Syst. 47(3): 1814-1836 (2011) - [j25]Matthieu Arzel, Cyril Lahuec, Christophe Jégo, Warren J. Gross, Yvain Bruned
Stochastic Multiple Stream Decoding of Cortex Codes. IEEE Trans. Signal Process. 59(7): 3486-3491 (2011) - [j24]Ali Naderi, Shie Mannor
Delayed Stochastic Decoding of LDPC Codes. IEEE Trans. Signal Process. 59(11): 5617-5626 (2011) - [j23]Saeed Sharifi Tehrani, Ali Naderi, Guy-Armand Kamendje, Shie Mannor
Tracking Forecast Memories for Stochastic Decoding. J. Signal Process. Syst. 63(1): 117-127 (2011) - [c21]Camille Leroux, Ido Tal, Alexander Vardy
Hardware architectures for successive cancellation decoding of polar codes. ICASSP 2011: 1665-1668 - [i2]Camille Leroux, Alexandre J. Raymond, Gabi Sarkis, Ido Tal, Alexander Vardy, Warren J. Gross:
Hardware Implementation of Successive Cancellation Decoders for Polar Codes. CoRR abs/1111.4362 (2011) - 2010
- [j22]Camille Leroux, Saied Hemati, Shie Mannor
Stochastic Chase Decoding of Reed-Solomon Codes. IEEE Commun. Lett. 14(9): 863-865 (2010) - [j21]Kevin Cushon
A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding. IEEE Trans. Circuits Syst. II Express Briefs 57-II(11): 893-897 (2010) - [j20]Saeed Sharifi Tehrani, Ali Naderi, Guy-Armand Kamendje, Saied Hemati, Shie Mannor
Majority-based tracking forecast memories for stochastic LDPC decoding. IEEE Trans. Signal Process. 58(9): 4883-4896 (2010) - [j19]Saeed Sharifi Tehrani, Chris Winstead, Warren J. Gross, Shie Mannor
Relaxation dynamics in stochastic iterative decoders. IEEE Trans. Signal Process. 58(11): 5955-5961 (2010) - [j18]Quang Trung Dong, Matthieu Arzel
Stochastic Decoding of Turbo Codes. IEEE Trans. Signal Process. 58(12): 6421-6425 (2010) - [c20]Gabi Sarkis, Saied Hemati, Shie Mannor
Relaxed half-stochastic decoding of LDPC codes over GF(q). Allerton 2010: 36-41 - [c19]François D. Côté, Ioannis N. Psaromiligkos, Warren J. Gross:
On the code tracking performance of GNSS modulation. CISS 2010: 1-5 - [c18]François Leduc-Primeau, Saied Hemati, Shie Mannor
Lowering Error Floors Using Dithered Belief Propagation. GLOBECOM 2010: 1-6 - [c17]Vincent C. Gaudet
Switching Activity in Stochastic Decoders. ISMVL 2010: 167-172 - [i1]Camille Leroux, Ido Tal, Alexander Vardy, Warren J. Gross:
Hardware architectures for Successive Cancellation Decoding of Polar Codes. CoRR abs/1011.2919 (2010)
2000 – 2009
- 2009
- [j17]Christophe Jégo, Warren J. Gross:
Turbo decoding of product codes using adaptive belief propagation. IEEE Trans. Commun. 57(10): 2864-2867 (2009) - [j16]Jahyun J. Koo, Alan C. Evans
3-D Brain MRI Tissue Classification on FPGAs. IEEE Trans. Image Process. 18(12): 2735-2746 (2009) - [c16]Bharathram Sivasubramanian, Warren J. Gross, Harry Leib:
Design and FPGA implementation of iterative decoders for codes on graphs. CCECE 2009: 1080-1084 - [c15]François Leduc-Primeau, Saied Hemati, Warren J. Gross, Shie Mannor
A Relaxed Half-Stochastic Iterative Decoder for LDPC Codes. GLOBECOM 2009: 1-6 - [c14]Saeed Sharifi Tehrani, Ali Naderi, Guy-Armand Kamendje, Shie Mannor
Tracking Forecast Memories in stochastic decoders. ICASSP 2009: 561-564 - [c13]Gabi Sarkis, Shie Mannor
Stochastic Decoding of LDPC Codes over GF(q). ICC 2009: 1-5 - [c12]Kevin Cushon
Bidirectional interleavers for LDPC decoders using transmission gates. SiPS 2009: 232-237 - 2008
- [j15]Laurier Boulianne, Sevin Al Assaad, Michel Dumontier
GridCell: a stochastic particle-based biological system simulator. BMC Syst. Biol. 2: 66 (2008) - [j14]Yousef El-Kurdi, David Fernández, Evgueni Souleimanov, Dennis Giannacopoulos, Warren J. Gross:
FPGA architecture and implementation of sparse matrix-vector multiplication for the finite element method. Comput. Phys. Commun. 178(8): 558-570 (2008) - [j13]Shaoqiang Bi, Warren J. Gross:
The Mixed-Radix Chinese Remainder Theorem and Its Applications to Residue Comparison. IEEE Trans. Computers 57(12): 1624-1632 (2008) - [j12]John Sachs Beeckler, Warren J. Gross:
Particle graphics on reconfigurable hardware. ACM Trans. Reconfigurable Technol. Syst. 1(3): 15:1-15:27 (2008) - [j11]Saeed Sharifi Tehrani, Shie Mannor
Fully Parallel Stochastic LDPC Decoders. IEEE Trans. Signal Process. 56(11): 5692-5703 (2008) - [j10]Saeed Sharifi Tehrani, Christophe Jégo, Bo Zhu, Warren J. Gross:
Stochastic Decoding of Linear Block Codes With High-Density Parity-Check Matrices. IEEE Trans. Signal Process. 56(11): 5733-5739 (2008) - [c11]Andrew J. Wong, Warren J. Gross:
Configurable Flow Models for FPGA Particle Graphics Engines. FCCM 2008: 283-284 - 2007
- [j9]Warren J. Gross, Frank R. Kschischang
Architecture and Implementation of an Interpolation Processor for Soft-Decision Reed-Solomon Decoding. IEEE Trans. Very Large Scale Integr. Syst. 15(3): 309-318 (2007) - [c10]Jahyun J. Koo, David Fernández, Ashraf Haddad, Warren J. Gross:
Evaluation of a High-Level-Language Methodology for High-Performance Reconfigurable Computers. ASAP 2007: 30-35 - [c9]Jahyun J. Koo, Alan C. Evans
Accelerating a Medical 3D Brain MRI Analysis Algorithm using a High-Performance Reconfigurable Computer. FPL 2007: 11-16 - [c8]Christophe Jégo, Warren J. Gross:
Turbo Decoding of Product Codes based on the Modified Adaptive Belief Propagation Algorithm. ISIT 2007: 641-644 - [c7]Saeed Sharifi Tehrani, Shie Mannor
Survey of Stochastic Computation on Factor Graphs. ISMVL 2007: 54 - [c6]Laurier Boulianne, Michel Dumontier, Warren J. Gross:
A stochastic particle-based biological system simulator. SCSC 2007: 794-801 - [c5]Saeed Sharifi Tehrani, Shie Mannor
An Area-Efficient FPGA-Based Architecture for Fully-Parallel Stochastic LDPC Decoding. SiPS 2007: 255-260 - 2006
- [j8]Saeed Sharifi Tehrani, Warren J. Gross, Shie Mannor
Stochastic decoding of LDPC codes. IEEE Commun. Lett. 10(10): 716-718 (2006) - [j7]Warren J. Gross, Frank R. Kschischang
Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Commun. 54(6): 1143 (2006) - [j6]Warren J. Gross, Frank R. Kschischang
Applications of Algebraic Soft-Decision Decoding of Reed-Solomon Codes. IEEE Trans. Commun. 54(7): 1224-1234 (2006) - [c4]Yousef El-Kurdi, Warren J. Gross, Dennis Giannacopoulos:
Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs. FCCM 2006: 293-294 - 2005
- [j5]Warren J. Gross, Frank R. Kschischang
Towards a VLSI Architecture for Interpolation-Based Soft-Decision Reed-Solomon Decoders. J. VLSI Signal Process. 39(1-2): 93-111 (2005) - [c3]John Sachs Beeckler, Warren J. Gross:
FPGA Particle Graphics Hardware. FCCM 2005: 85-94 - [c2]Shaoqiang Bi, Warren J. Gross, Wei Wang, Asim J. Al-Khalili, M. N. S. Swamy:
An Area-Reduced Scheme for Modulo 2n-1 Addition/Subtraction. IWSOC 2005: 396-399 - 2004
- [c1]Warren J. Gross, Frank R. Kschischang
An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding. FCCM 2004: 310-311 - 2003
- [j4]Emmanuel Boutillon, Warren J. Gross, P. Glenn Gulak:
VLSI architectures for the MAP algorithm. IEEE Trans. Commun. 51(2): 175-185 (2003) - 2001
- [j3]Warren J. Gross, Dragica Vasileska
Ultra-small MOSFETs: The Importance of the Full Coulomb Interaction on Device Characteristics. VLSI Design 13(1-4): 75-78 (2001) - 2000
- [j2]Warren J. Gross, Dragica Vasileska
3D Simulations of Ultra-small MOSFETs with Real-space Treatment of the Electron - Electron and Electron-ion Interactions. VLSI Design 10(4): 437-452 (2000)
1990 – 1999
- 1998
- [j1]Dragica Vasileska
Convergence Properties of the Bi-CGSTAB Method for the Solution of the 3D Poisson and 3D Electron Current Continuity Equations for Scaled Si MOSFETs. VLSI Design 8(1-4): 301-305 (1998)
Coauthor Index
[j98] [j94] [i59] [j88] [j86] [j84] [j82] [c101] [i51] [j79] [j78] [j77] [j75] [c94] [c92] [c91] [c87] [c86] [c84] [i47] [i46] [i43] [j69] [j67] [j66] [j65] [c83] [c82] [c79] [c76] [c74] [c73] [c72] [i36] [i34] [i33] [i31] [i29] [i27] [i26] [i25] [j59] [c68] [c63] [c62] [i22] [i21] [i19] [c57] [c49]
[j115] [j112] [j108] [j100] [c127] [c124] [i66] [i65] [i63] [i61] [c117] [i56] [j88] [j84] [c109] [c106] [c104] [c101] [c99] [i51] [i50] [i49] [i48] [j75] [c96] [c94] [c90] [c85] [i47] [i45] [i44] [i39] [j69] [j67] [j65] [c83] [c82] [c78] [c74] [c72] [i36] [i34] [i33] [i32] [i31] [i29] [i27] [j59] [c67] [c63] [c62] [c57] [i12]
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