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Jürgen Bömmels
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2020 – today
- 2024
- [c10]Steven Demuynck, Victor Vega-Gonzalez, C. Toledo de Carvalho Cavalcante, L. Petersen Barbosa Lima, K. Stiers, C. Sheng, A. Vandooren, M. Hosseini, X. Zhou, Hans Mertens, Thomas Chiarella, Jürgen Bömmels, Roger Loo, E. Rosseel, Clement Porret, Y. Shimura, A. Akula, G. Mannaert, S. Choudhury, V. Brissonneau, E. Dupuy, T. Sarkar, Nathali Franchina-Vergel, A. Peter, Nicolas Jourdan, J. P. Soulie, Kevin Vandersmissen, F. Sebaai, P. Puttarame Gowda, K. Lai, A. Mingardi, S. Sumar Sarkar, K. D'Have, B. T. Chan, A. Sepulveda Marquez, R. Langer, I. Gyo Koo, E. Altamirano Sanchez, Katia Devriendt, P. Rincon Delgadillo, F. Lazzarino, Jérôme Mitard, J. Geypen, E. Grieten, D. Batuk, Y.-F. Chen, F. Verbeek, F. Holsteyns, S. Subramanian, N. Horiguchi, S. Biesemans:
Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j5]Dawit Burusie Abdi
, Shairfe Muhammad Salahuddin
3D SRAM Macro Design in 3D Nanofabric Process Technology. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2858-2867 (2023) - [c9]Hans Mertens, M. Hosseini, Thomas Chiarella, D. Zhou, S. Wang, G. Mannaert, E. Dupuy, D. Radisic, Z. Tao, Yusuke Oniki, Andriy Hikavyy, R. Rosseel, A. Mingardi, S. Choudhury, P. Puttarame Gowda, F. Sebaai, A. Peter, Kevin Vandersmissen, J. P. Soulie, An De Keersgieter, L. Petersen Barbosa Lima, C. Cavalcante, D. Batuk, G. T. Martinez, J. Geypen, F. Seidel, K. Paulussen, P. Favia, Jürgen Bömmels, Roger Loo
Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning. VLSI Technology and Circuits 2023: 1-2 - [c8]Victor Vega-Gonzalez, D. Radisic, Bt Chan, S. Choudhury, S. Wang, A. Mingardi, Q. Toan Le, H. Decoster, Yusuke Oniki, P. Puttarame, Kevin Vandersmissen, J. P. Soulie, A. Peter, A. Sepulveda, D. Batuk, G. T. Martinez, Olivier Richard, Jürgen Bömmels, S. Biesemans, E. Dentoni Litta, Naoto Horiguchi, Seongho Park, Zsolt Tokei:
Integration of a Stacked Contact MOL for Monolithic CFET. VLSI Technology and Circuits 2023: 1-2 - 2020
- [c7]Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon:
Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow. VLSI-SOC 2020: 34-39 - [c6]Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon:
3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs. VLSI-SoC (Selected Papers) 2020: 279-300
2010 – 2019
- 2017
- [j4]Luka Kljucar, Mario Gonzalez, Kristof Croes, Ingrid De Wolf, Joke De Messemaeker, Gayle Murdoch, Philip Nolmans, Joeri De Vos, Jürgen Bömmels, Eric Beyne
Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects. Microelectron. Reliab. 79: 297-305 (2017) - 2016
- [j3]Luka Kljucar, Mario Gonzalez, Ingrid De Wolf, Kristof Croes, Jürgen Bömmels, Zsolt Tökei
Evaluation of via density and low-k Young's modulus influence on mechanical performance of advanced node multi-level Back-End-Of-Line. Microelectron. Reliab. 56: 93-100 (2016) - [j2]Houman Zahedmanesh, Mario Gonzalez, Ivan Ciofi, Kristof Croes, Jürgen Bömmels, Zsolt Tökei
Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation. Microelectron. Reliab. 59: 102-107 (2016) - 2015
- [c5]Kris Croes, Alicja Lesniewska, Chen Wu, Ivan Ciofi, Agnieszka Banczerowska, B. Briggs, S. Demuynck, Zsolt Tökei, Jürgen Bömmels, Yves Saad, W. Gao:
Intrinsic reliability of local interconnects for N7 and beyond. IRPS 2015: 2 - [c4]Baojun Tang, Kris Croes, Nicolas Jourdan, Jürgen Bömmels, Zsolt Tökei
Constant voltage electromigration for advanced BEOL copper interconnects. IRPS 2015: 2 - [c3]Kris Croes, Deniz Kocaay, Ivan Ciofi, Jürgen Bömmels, Zsolt Tökei:
Impact of process variability on BEOL TDDB lifetime model assessment. IRPS 2015: 5 - 2014
- [j1]Baojun Tang, Kris Croes, Yohan Barbarin, Yunqi Wang, Robin Degraeve, Yunlong Li, Maria Toledano-Luque, Thomas Kauerauf, Jürgen Bömmels, Zsolt Tökei
As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability. Microelectron. Reliab. 54(9-10): 1675-1679 (2014) - [c2]Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, Mircea Dusa, Arindam Mallik, Sushil Sakhare, Boris Vandewalle, Piet Wambacq, Bharani Chava
Design Technology co-optimization for N10. CICC 2014: 1-8 - [c1]Trong Huynh Bao
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. ESSDERC 2014: 102-105
Coauthor Index
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