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Sun-Il Hwang

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2010 – 2019

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2018
[j5]
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Min-Jae Seo, Dong-Hwan Jin, Ye-Dam Kim, Sun-Il Hwang, Jong-Pal Kim, Seung-Tak Ryu:
A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3617-3627 (2018)
2017
[j4]
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Hyeon-June Kim, Sun-Il Hwang, Jae-Hyun Chung, Jong-Ho Park, Seung-Tak Ryu:
A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction. IEEE J. Solid State Circuits 52(9): 2488-2497 (2017)
2016
[j3]
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Wan Kim, Hyeok-Ki Hong, Yi-Ju Roh, Hyun-Wook Kang, Sun-Il Hwang, Dong-Shin Jo, Dong-Jin Chang, Min-Jae Seo, Seung-Tak Ryu:
A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. IEEE J. Solid State Circuits 51(8): 1826-1839 (2016)
[j2]
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Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, Seung-Tak Ryu:
A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs. IEEE J. Solid State Circuits 51(10): 2262-2273 (2016)
2015
[j1]
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Dong-Hwan Jin, Ji-Wook Kwon, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Junho Cheon, Seung-Tak Ryu:
A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory. IEEE J. Solid State Circuits 50(10): 2431-2440 (2015)
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Hyeon-June Kim, Sun-Il Hwang, Ji-Wook Kwon, Dong-Hwan Jin, Byoung Soo Choi, Sang-Gwon Lee, Jong-Ho Park, Jang-Kyoo Shin, Seung-Tak Ryu:
Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs. A-SSCC 2015: 1-4
2014
[c1]
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Ji-Wook Kwon, Dong-Hwan Jin, Hyeon-June Kim, Sun-Il Hwang, Min-Chul Shin, Jong-Ho Kang, Seung-Tak Ryu:
A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. CICC 2014: 1-4

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