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Arjun Ramaswami Palaniappan

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2010 – 2019

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2019
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Arjun Ramaswami Palaniappan, Liter Siek:
A TDC-less all-digital phase locked loop for medical implant applications. Microprocess. Microsystems 69: 168-178 (2019)
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Arjun Ramaswami Palaniappan, Liter Siek:
A 0.6 V, 1.74 ps Resolution Capacitively Boosted Time-to-Digital Converter in 180 nm CMOS. ISCAS 2019: 1-4
2018
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Arjun Ramaswami Palaniappan, Liter Siek:
A 0.0186 mm², 0.65 V Supply, 9.53 ps RMS Jitter All-Digital PLL for Medical Implants. NORCAS 2018: 1-4
2016
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  - conf/isicir/TehPSZ16
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Jian Sen Teh, Arjun Ramaswami Palaniappan, Liter Siek, Yuanjin Zheng:
Review of pulse generators for gated ring oscillator based Time-to-Digital converters. ISIC 2016: 1-4
2015
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Arjun Ramaswami Palaniappan, Dominic Maurath, Felix Kalathiparambil, Liter Siek:
A higher order curvature corrected 2 ppm/°C CMOS voltage reference circuit. ISCAS 2015: 505-508

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