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Gaurav Narang
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2020 – today
- 2024
- [j3]Chukwufumnanya Ogbogu
, Gaurav Narang
HuNT: Exploiting Heterogeneous PIM Devices to Design a 3-D Manycore Architecture for DNN Training. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(11): 3300-3311 (2024) - [j2]Gaurav Narang
TEFLON: Thermally Efficient Dataflow-aware 3D NoC for Accelerating CNN Inferencing on Manycore PIM Architectures. ACM Trans. Embed. Comput. Syst. 23(5): 78:1-78:23 (2024) - [c5]Harsh Sharma, Gaurav Narang, Janardhan Rao Doppa, Ümit Y. Ogras, Partha Pratim Pande:
Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads. DATE 2024: 1-6 - [i1]Harsh Sharma, Gaurav Narang, Janardhan Rao Doppa, Ümit Y. Ogras, Partha Pratim Pande:
Dataflow-Aware PIM-Enabled Manycore Architecture for Deep Learning Workloads. CoRR abs/2403.19073 (2024) - 2023
- [j1]Gaurav Narang
Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework. ACM Trans. Design Autom. Electr. Syst. 28(5): 84:1-84:21 (2023) - [c4]Gaurav Narang, Raid Ayoub, Michael Kishinevsky, Janardhan Rao Doppa, Partha Pratim Pande:
Uncertainty-Aware Online Learning for Dynamic Power Management in Large Manycore Systems. ISLPED 2023: 1-6
2010 – 2019
- 2016
- [c3]Prakhar Raj Gupta, G. S. Visweswaran, Gaurav Narang, Anuj Grover
Heterogeneous memory assembly exploration using a floorplan and interconnect aware framework. SoCC 2016: 290-295 - 2015
- [c2]Gaurav Narang, Alexander Fell
Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems. SoCC 2015: 105-110 - [c1]Gaurav Narang, Pragya Sharma, Mansi Jain, Anuj Grover
Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance. VLSID 2015: 411-416
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