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Deepak Kachave
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2010 – 2019
- 2019
- [j7]Anirban Sengupta
, Deepak Kachave
Low Cost Functional Obfuscation of Reusable IP Ores Used in CE Hardware Through Robust Locking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 604-616 (2019) - 2018
- [j6]Deepak Kachave, Anirban Sengupta:
Shielding CE Hardware Against Reverse-Engineering Attacks Through Functional Locking [Hardware Matters]. IEEE Consumer Electron. Mag. 7(2): 111-114 (2018) - [j5]Anirban Sengupta, Deepak Kachave:
Forensic engineering for resolving ownership problem of reusable IP core generated during high level synthesis. Future Gener. Comput. Syst. 80: 29-46 (2018) - [j4]Deepak Kachave, Anirban Sengupta, Shubha Neema, Panugothu Sri Harsha:
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation. IET Comput. Digit. Tech. 12(6): 268-278 (2018) - [j3]Anirban Sengupta
Spatial and Temporal Redundancy for Transient Fault-Tolerant Datapath. IEEE Trans. Aerosp. Electron. Syst. 54(3): 1168-1183 (2018) - [c4]Anirban Sengupta, Deepak Kachave:
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores. iSES 2018: 17-20 - 2017
- [j2]Anirban Sengupta, Deepak Kachave:
Low cost fault tolerance against kc-cycle and km-unit transient for loop based control data flow graphs during physically aware high level synthesis. Microelectron. Reliab. 74: 88-99 (2017) - [c3]Anirban Sengupta, Deepak Kachave, Shubha Neema, Panugothu Sri Harsha:
Reliability and Threat Analysis of NBTI Stress on DSP Cores. iNIS 2017: 11-14 - 2016
- [j1]Deepak Kachave, Anirban Sengupta:
Integrating physical level design and high level synthesis for simultaneous multi-cycle transient and multiple transient fault resiliency of application specific datapath processors. Microelectron. Reliab. 60: 141-152 (2016) - [c2]Deepak Kachave, Anirban Sengupta:
Protecting Ownership of Reusable IP Core Generated during High Level Synthesis. iNIS 2016: 80-82 - [c1]Anirban Sengupta, Deepak Kachave:
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis. ISVLSI 2016: 75-80
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