Process-insensitive low-power design of switched-capacitor integrators. - Naiknaware, Ravindranath; Fiez, Terri S. (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

142 dB ΔΣ ADC with a 100 nV LSB in a 3 V CMOS process. - Naiknaware, Ravindranath; Fiez, Terri S. (2000)

Automated Hierarchical Cmos Analog Circuit Stack Generation with Intramodule Connectivity and Matching Considerations. - Naiknaware, Ravindranath; Fiez, Terri S. (IEEE J. Solid State Circuits, 1999)

Automated hierarchical CMOS analog circuit stack generation with intramodule connectivity and matching considerations. - Naiknaware, Ravindranath; Fiez, Terri S. (IEEE J. Solid State Circuits, 1999)

Time-referenced single-path multi-bit Sigma-Delta ADC using a VCO based quantizer. - Naiknaware, Ravindranath; Fiez, Terri S. (1999)

Switched-capacitor integrator design optimizing for power and process variations. - Naiknaware, Ravindranath; Fiez, Terri S. (1999)

Schematic driven module generation for analog circuits with performance optimization and matching considerations. - Naiknaware, Ravindranath; Fiez, Terri S. (1998)

CMOS analog circuit stack generation with matching constraints. - Naiknaware, Ravindranath; Fiez, Terri S. (1998)

Analog Automatic Test Plan Generator - Integrating with Modular Analog IC Design Environment. - Naiknaware, Ravindranath (1993)

Automatic Test Plan Generation for Analog and Mixed Signal Integrated Circuits using Partial Activation and High Level Simulation. - Naiknaware, Ravindranath; Nandakumar, G. N.; Kasa, Srinivasa Rao (1993)

Automatic Test Plan Generation for Analog Integrated Circuits - A Practical Approach. - Naiknaware, Ravindranath; Nandakumar, G. N.; Arora, Rajeev; Larkin, John (1993)