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Bing-Yang Lin
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2020 – today
- 2024
- [c13]Bing-Yang Lin, Sebastian Müller, Luigi Vigneri, Ching-Hua Lin:
Evaluating Blockchain Consensus Mechanisms: A Comprehensive Three-Tiered Approach with Application to IOTA 2.0. BLOCKCHAIN 2024: 150-159 - 2023
- [c12]Bing-Yang Lin, Daria Dziubaltowska
, Piotr Macek, Andreas Penzkofer, Sebastian Müller:
TangleSim: An Agent-based, Modular Simulator for DAG-based Distributed Ledger Technologies. ICBC 2023: 1-5 - [i2]Bing-Yang Lin, Daria Dziubaltowska, Piotr Macek, Andreas Penzkofer, Sebastian Müller:
TangleSim: An Agent-based, Modular Simulator for DAG-based Distributed Ledger Technologies. CoRR abs/2305.01232 (2023) - 2022
- [c11]Bing-Yang Lin, Daria Dziubaltowska
Robustness of the Tangle 2.0 Consensus. VALUETOOLS 2022: 259-276 - [i1]Bing-Yang Lin, Daria Dziubaltowska
Robustness of the Tangle 2.0 Consensus. CoRR abs/2208.08254 (2022)
2010 – 2019
- 2017
- [j7]Zhi-Yong Liu
Controller Architecture for Low-Power, Low-Latency DRAM With Built-in Cache. IEEE Des. Test 34(2): 69-78 (2017) - [j6]Kai-Li Wang
Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Des. Test 34(3): 50-58 (2017) - [j5]Hsuan-Hung Liu, Bing-Yang Lin, Cheng-Wen Wu
A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. IEEE Trans. Computers 66(8): 1293-1301 (2017) - [c10]Bing-Yang Lin, Hsin-Wei Hung, Shu-Mei Tseng, Chi Chen, Cheng-Wen Wu
Highly reliable and low-cost symbiotic IOT devices and systems. ITC 2017: 1-10 - [c9]Cheng-Wen Wu
Symbiotic system models for efficient IGT system design and test. ITC-Asia 2017: 71-76 - 2016
- [j4]Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu
Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. IEEE Des. Test 33(2): 30-39 (2016) - [j3]Bing-Yang Lin, Cheng-Wen Wu
A Local Parallel Search Approach for Memory Failure Pattern Identification. IEEE Trans. Computers 65(3): 770-780 (2016) - [c8]Hsuan-Wei Liu, Bing-Yang Lin, Cheng-Wen Wu
Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test. ATS 2016: 156-160 - [c7]Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu
Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. DAC 2016: 58:1-58:6 - [c6]Sin-Yu Wei, Bing-Yang Lin, Cheng-Wen Wu
A fast sweep-line-based failure pattern extractor for memory diagnosis. ETS 2016: 1-6 - 2015
- [c5]Bing-Yang Lin, Cheng-Wen Wu
System-level test coverage prediction by structural stress test data mining. VLSI-DAT 2015: 1-4 - 2014
- [j2]Min-Xiou Chen, Bing-Yang Lin:
Location service and session mobility for streaming media applications in home networks. Comput. Stand. Interfaces 36(2): 368-379 (2014) - [j1]Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu
On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs. IEEE Des. Test 31(4): 16-26 (2014) - [c4]Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu
Redundancy architectures for channel-based 3D DRAM yield improvement. ITC 2014: 1-7 - 2013
- [c3]Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu
Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints. Asian Test Symposium 2013: 1-6 - 2012
- [c2]Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu
A Memory Failure Pattern Analyzer for memory diagnosis and repair. VTS 2012: 234-239 - 2010
- [c1]Min-Xiou Chen, Bing-Yang Lin, Wen-Yen Weng:
Supporting Multimedia Applications in Home Networks using SIP and SLP. DCNET/OPTICS 2010: 19-24
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