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Pasquale Davide Schiavone
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2020 – today
- 2024
- [c12]Nicolò Carpentieri
, Juan Sapriza
Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA. CF (Companion) 2024 - [c11]Anna Burdina
Cross-layer Exploration of 2.5D Energy-Efficient Heterogeneous Chiplets Integration: From System Simulation to Open Hardware. ISLPED 2024: 1-6 - [i11]Simone Machetti
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller for the Exploration of Ultra-Low-Power Edge Accelerators. CoRR abs/2401.05548 (2024) - [i10]Nicolò Carpentieri, Juan Sapriza, Pasquale Davide Schiavone, Daniele Jahier Pagliari, David Atienza, Maurizio Martina, Alessio Burrello:
Performance evaluation of acceleration of convolutional layers on OpenEdgeCGRA. CoRR abs/2403.01236 (2024) - [i9]Daniel Vázquez, Jose Miranda, Alfonso Rodríguez, Andrés Otero, Pasquale Davide Schiavone, David Atienza:
STRELA: STReaming ELAstic CGRA Accelerator for Embedded Systems. CoRR abs/2404.12503 (2024) - [i8]Dimitrios Samakovlis, Stefano Albini, Rubén Rodríguez Álvarez, Denisa-Andreea Constantinescu, Pasquale Davide Schiavone, Miguel Peón Quirós, David Atienza:
BiomedBench: A benchmark suite of TinyML biomedical applications for low-power wearables. CoRR abs/2406.03886 (2024) - [i7]Michele Caon, Clément Choné, Pasquale Davide Schiavone, Alexandre Levisse, Guido Masera, Maurizio Martina, David Atienza:
Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes. CoRR abs/2406.14263 (2024) - [i6]Alireza Amirshahi, Maedeh H. Toosi, Siamak Mohammadi, Stefano Albini, Pasquale Davide Schiavone, Giovanni Ansaloni, Amir Aminifar, David Atienza:
MetaWearS: A Shortcut in Wearable Systems Lifecycle with Only a Few Shots. CoRR abs/2408.01988 (2024) - 2023
- [c10]Pasquale Davide Schiavone
X-HEEP: An Open-Source, Configurable and Extendible RISC-V Microcontroller. CF 2023: 379-380 - 2022
- [c9]Mattia Orlandi
sEMG Neural Spikes Reconstruction for Gesture Recognition on a Low-Power Multicore Processor. BioCAS 2022: 704-708 - [c8]Mattia Orlandi
Motor-Unit Ordering of Blindly-Separated Surface-EMG Signals for Gesture Recognition. SYSINT 2022: 518-529 - 2021
- [j6]Pasquale Davide Schiavone
Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 677-690 (2021) - [c7]Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini:
Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores. ISCAS 2021: 1-5 - 2020
- [j5]Alfio Di Mauro
Always-On 674μ W@4GOP/s Error Resilient Binary Neural Networks With Aggressive SRAM Voltage Scaling on a 22-nm IoT End-Node. IEEE Trans. Circuits Syst. 67-I(11): 3905-3918 (2020) - [c6]Pasquale Davide Schiavone, Davide Rossi, Yan Liu, Simone Benatti
Neuro-PULP: A Paradigm Shift Towards Fully Programmable Platforms for Neural Interfaces. AICAS 2020: 50-54 - [i5]Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini:
Arnold: an eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End-Nodes. CoRR abs/2006.14256 (2020) - [i4]Alfio Di Mauro, Francesco Conti, Pasquale Davide Schiavone, Davide Rossi, Luca Benini:
Always-On 674uW @ 4GOP/s Error Resilient Binary Neural Networks with Aggressive SRAM Voltage Scaling on a 22nm IoT End-Node. CoRR abs/2007.08952 (2020)
2010 – 2019
- 2019
- [c5]Annachiara Ruospo
On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification. DFT 2019: 1-6 - 2018
- [j4]Victor Javier Kartsch, Simone Benatti
A sensor fusion approach for drowsiness detection in wearable ultra-low-power systems. Inf. Fusion 43: 66-76 (2018) - [j3]Francesco Conti
XNOR Neural Engine: A Hardware Accelerator IP for 21.6-fJ/op Binary Neural Network Inference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(11): 2940-2951 (2018) - [c4]Michael Hersche
Fast and Accurate Multiclass Inference for MI-BCIs Using Large Multiscale Temporal and Spectral Features. EUSIPCO 2018: 1690-1694 - [c3]Pasquale Davide Schiavone, Ernesto Sánchez, Annachiara Ruospo
An Open-Source Verification Framework for Open-Source Cores: A RISC-V Case Study. VLSI-SoC 2018: 43-48 - [i3]Francesco Conti, Pasquale Davide Schiavone, Luca Benini:
XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference. CoRR abs/1807.03010 (2018) - 2017
- [j2]Francesco Conti
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2481-2494 (2017) - [j1]Michael Gautschi
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2700-2713 (2017) - [c2]Pasquale Davide Schiavone, Francesco Conti, Davide Rossi, Michael Gautschi, Antonio Pullini, Eric Flamand, Luca Benini
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications. PATMOS 2017: 1-8 - 2016
- [i2]Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini:
A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices. CoRR abs/1608.08376 (2016) - [i1]Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini:
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. CoRR abs/1612.05974 (2016) - 2015
- [c1]Riccardo Cantoro
An evolutionary approach for test program compaction. LATS 2015: 1-6
Coauthor Index
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