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Davide Bellizia
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2020 – today
- 2023
- [j20]Ofek Gur, Tomer Gross, Davide Bellizia
, François-Xavier Standaert
An In-Depth Evaluation of Externally Amplified Coupling (EAC) Attacks - A Concrete Threat for Masked Cryptographic Implementations. IEEE Trans. Circuits Syst. I Regul. Pap. 70(2): 783-796 (2023) - 2022
- [j19]Itamar Levi
Tight-ES-TRNG: Improved Construction and Robustness Analysis. SN Comput. Sci. 3(4): 321 (2022) - [j18]Riccardo Della Sala
High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4886-4897 (2022) - [j17]Riccardo Della Sala
A Novel Ultra-Compact FPGA-Compatible TRNG Architecture Exploiting Latched Ring Oscillators. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 1672-1676 (2022) - [j16]Riccardo Della Sala
A Lightweight FPGA Compatible Weak-PUF Primitive Based on XOR Gates. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2972-2976 (2022) - [j15]Davide Bellizia, Clément Hoffmann
When Bad News Become Good News Towards Usable Instances of Learning with Physical Errors. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2022(4): 1-24 (2022) - 2021
- [j14]Davide Bellizia
SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks. Cryptogr. 5(3): 16 (2021) - [j13]Riccardo Della Sala
A Novel Ultra-Compact FPGA PUF: The DD-PUF. Cryptogr. 5(3): 23 (2021) - [j12]Dina Kamel
Side-channel analysis of a learning parity with physical noise processor. J. Cryptogr. Eng. 11(2): 171-179 (2021) - [j11]Davide Bellizia
Learning Parity with Physical Noise: Imperfections, Reductions and FPGA Prototype. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(3): 390-417 (2021) - [c12]Davide Bellizia, Balazs Udvarhelyi, François-Xavier Standaert:
Towards a Better Understanding of Side-Channel Analysis Measurements Setups. CARDIS 2021: 64-79 - [c11]Davide Bellizia, Nadia El Mrabet, Apostolos P. Fournaris, Simon Pontié, Francesco Regazzoni
Post-Quantum Cryptography: Challenges and Opportunities for Robust and Secure HW Design. DFT 2021: 1-6 - 2020
- [j10]Itamar Levi
Beyond algorithmic noise or how to shuffle parallel implementations? Int. J. Circuit Theory Appl. 48(5): 674-695 (2020) - [j9]Davide Bellizia
SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(7): 2317-2330 (2020) - [j8]Itamar Levi
Ask Less, Get More: Side-Channel Signal Hiding, Revisited. IEEE Trans. Circuits Syst. 67-I(12): 4904-4917 (2020) - [j7]Davide Bellizia
Spook: Sponge-Based Leakage-Resistant Authenticated Encryption with a Masked Tweakable Block Cipher. IACR Trans. Symmetric Cryptol. 2020(S1): 295-349 (2020) - [c10]Davide Bellizia, Olivier Bronchain, Gaëtan Cassiers, Vincent Grosso, Chun Guo, Charles Momin, Olivier Pereira, Thomas Peters, François-Xavier Standaert
Mode-Level vs. Implementation-Level Physical Security in Symmetric Cryptography - A Practical Guide Through the Leakage-Resistance Jungle. CRYPTO (1) 2020: 369-400 - [c9]Melissa Azouaoui, Davide Bellizia, Ileana Buhan, Nicolas Debande, Sébastien Duval
A Systematic Appraisal of Side Channel Evaluation Strategies. SSR 2020: 46-66 - [i2]Davide Bellizia, Olivier Bronchain, Gaëtan Cassiers, Vincent Grosso, Chun Guo, Charles Momin, Olivier Pereira, Thomas Peters, François-Xavier Standaert:
Mode-Level vs. Implementation-Level Physical Security in Symmetric Cryptography: A Practical Guide Through the Leakage-Resistance Jungle. IACR Cryptol. ePrint Arch. 2020: 211 (2020) - [i1]Melissa Azouaoui
A Systematic Appraisal of Side Channel Evaluation Strategies. IACR Cryptol. ePrint Arch. 2020: 1347 (2020)
2010 – 2019
- 2019
- [j6]Itamar Levi, Davide Bellizia
Reducing a Masked Implementation's Effective Security Order with Setup Manipulations And an Explanation Based on Externally-Amplified Couplings. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2019(2): 293-317 (2019) - 2018
- [j5]Davide Bellizia, Giuseppe Scotti
TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(11): 3874-3884 (2018) - [j4]Davide Bellizia
Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks. IEEE Trans. Very Large Scale Integr. Syst. 26(7): 1368-1376 (2018) - [c8]Dina Kamel, Davide Bellizia, François-Xavier Standaert
Demonstrating an LPPN Processor. ASHES@CCS 2018: 18-23 - [c7]Davide Bellizia
Secure Implementation of TEL-compatible Flip-Flops using a Standard-Cell Approach. ISCAS 2018: 1-5 - [c6]Davide Bellizia, Gaetano Palumbo, Giuseppe Scotti, Alessandro Trifiletti:
A Novel Very Low Voltage Topology to implement MCML XOR Gates. PRIME 2018: 157-160 - 2017
- [j3]Davide Bellizia
Template attacks exploiting static power and application to CMOS lightweight crypto-hardware. Int. J. Circuit Theory Appl. 45(2): 229-241 (2017) - [j2]Davide Bellizia
Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications. IEEE Trans. Emerg. Top. Comput. 5(3): 329-339 (2017) - [j1]Giuseppe Scotti
Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3509-3520 (2017) - [c5]Milena Djukanovic, Davide Bellizia
Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications. AFRICACRYPT 2017: 79-94 - [c4]Davide Bellizia
Novel measurements setup for attacks exploiting static power using DC pico-ammeter. ECCTD 2017: 1-4 - [c3]Davide Bellizia
VHDL implementation of FWL RLS algorithm. ECCTD 2017: 1-4 - 2016
- [c2]Davide Bellizia
Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to Side Channel Attacks Exploiting Static Power. MIXDES 2016: 211-216 - [c1]Davide Bellizia
On-chip analog current equalizer as a countermeasure against side-channel attacks in CMOS nanometer technology. MIXDES 2016: 229-234
Coauthor Index
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