A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET - James Hudner; Declan Carey; Ronan Casey; Kay Hearne; Pedro Wilson de Abreu Farias Neto; Ilias Chlis; Marc Erett; Chi Fung Poon; Asma Laraba; Hongtao Zhang; Sai Lalith Chaitanya Ambatipudi; David Mahashin; et al. (2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018, 2018)

A 0.5-16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET - Marc Erett; James Hudner; Declan Carey; Ronan Casey; Kevin Geary; Kay Hearne; Pedro Neto; Thomas Mallard; Vikas Sooden; Mark Smyth; Yohan Frans; Jay Im; et al. (IEEE J. Solid State Circuits, 2017)

A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET - Marc Erett; James Hudner; Declan Carey; Ronan Casey; Kevin Geary; Kay Hearne; Pedro Neto; Thomas Mallard; Vikas Sooden; Mark Smyth; Yohan Frans; Jay Im; et al. (ESSCIRC Conference 2016: 42\(^nd\) European Solid-State Circuits Conference, Lausanne, Switzerland, September 12-15, 2016, 2016)