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Denis Teixeira Franco
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2010 – 2019
- 2019
- [c15]Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa, Paulo F. Butzen
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An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults. VLSI-SoC (Selected Papers) 2019: 69-88 - [c14]Rafael B. Schvittz, Denis Teixeira Franco, Leomar Soares, Paulo Francisco Butzen
A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates. VLSI-SoC 2019: 185-190 - 2018
- [c13]Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa Jr., Paulo F. Butzen
Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults. ICECS 2018: 357-360 - [c12]Matheus F. Pontes
The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits. ICECS 2018: 433-436 - [c11]Rafael B. Schvittz, Matheus F. Pontes, Cristina Meinhardt
Reliability evaluation of circuits designed in multi- and single-stage versions. LASCAS 2018: 1-4 - 2017
- [c10]Gabriel S. Porto, Paulo F. Butzen
Exploring BDDs to reduce test pattern set. LATS 2017: 1-4 - 2016
- [c9]Rafael B. Schivittz, Denis Teixeira Franco, Cristina Meinhardt
A probabilistic model for stuck-on faults in combinational logic gates. LATS 2016: 39-44 - [c8]Rafael B. Schivittz, Rafael Fritz, Denis Teixeira Franco, Lirida A. B. Naviner
Inserting permanent fault input dependence on PTM to improve robustness evaluation. SBCCI 2016: 1-6 - 2013
- [c7]Leonardo Martins Rodrigues
A system based on interval fuzzy approach to predict the appearance of pests in agriculture. IFSA/NAFIPS 2013: 1262-1267 - 2010
- [c6]Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner
On evaluating the signal reliability of self-checking arithmetic circuits. SBCCI 2010: 109-114
2000 – 2009
- 2008
- [j4]Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner
Signal probability for reliability evaluation of logic circuits. Microelectron. Reliab. 48(8-9): 1586-1591 (2008) - [j3]Maí Correia R. de Vasconcelos, Denis Teixeira Franco, Lirida A. B. Naviner
Relevant metrics for evaluation of concurrent error detection schemes. Microelectron. Reliab. 48(8-9): 1601-1603 (2008) - [c5]Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner
Reliability analysis of logic circuits based on signal probability. ICECS 2008: 670-673 - [c4]Maí Correia R. de Vasconcelos, Denis Teixeira Franco, Lirida A. B. Naviner
On the output events in concurrent error detection schemes. ICECS 2008: 978-981 - [i1]Lirida Alves de Barros Naviner, Jean-François Naviner, Denis Teixeira Franco, Maí Correia R. de Vasconcelos:
Methods and Metrics for Reliability Assessment. Fault-Tolerant Distributed Algorithms on VLSI Chips 2008 - 2006
- [j2]Denis Teixeira Franco, Jean-François Naviner
Yield and reliability issues in nanoelectronic technologies. Ann. des Télécommunications 61(11-12): 1422-1457 (2006) - 2003
- [j1]Luigi Carro
Circuit-Level Considerations for Mixed-Signal Programmable Components. IEEE Des. Test Comput. 20(1): 76-84 (2003) - 2000
- [c3]Luigi Carro, Adão Antônio de Souza Jr.
Non-Linear Components for Mixed Circuits Analog Front-End. DATE 2000: 544-549 - [c2]Luigi Carro, Denis Teixeira Franco:
FPGA Based Systems with Linear and Non-Linear Signal Processing Capabilities. EUROMICRO 2000: 1260- - [c1]Denis Teixeira Franco, Luigi Carro:
FPGA Architecture Comparison for Non-Conventional Signal Processing. IJCNN (2) 2000: 55-58
Coauthor Index
aka: Lirida Alves de Barros Naviner
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