Array Architectures for 3-D NAND Flash Memories - Rino Micheloni; Seiichi Aritome; Luca Crippa (Proc. IEEE, 2017)

Study of error repeatability and recovery in 40nm TaOx ReRAM - Takashi Inose; Seiichi Aritome; Ryutaro Yasuhara; Satoshi Mishima; Ken Takeuchi (47th European Solid-State Device Research Conference, ESSDERC 2017, Leuven, Belgium, September 11-14, 2017, 2017)

A 130-mm/\(^2\), 256-Mbit NAND flash with shallow trench isolation technology - Kenichi Imamiya; Yoshihisa Sugiura; Hiroshi Nakamura; Toshihiko Himeno; Ken Takeuchi; Tamio Ikehashi; Kazushige Kanda; Koji Hosono; Riichiro Shirota; Seiichi Aritome; Kazuhiro Shimizu; Kazuo Hatakeyama; et al. (IEEE J. Solid State Circuits, 1999)

A compact on-chip ECC for low cost flash memories - Toru Tanzawa; Tomoharu Tanaka; Ken Takeuchi; Riichiro Shirota; Seiichi Aritome; Hiroshi Watanabe; Gertjan Hemink; Kazuhiro Shimizu; Shinji Sato; Yuji Takeuchi; Kazunori Ohuchi (IEEE J. Solid State Circuits, 1997)

BiCMOS circuit technology for high-speed DRAMs - Shigeyoshi Watanabe; Koji Sakui; Tsuneaki Fuse; Takahiko Hara; Seiichi Aritome; Katsuhiko Hieda (IEEE J. Solid State Circuits, 1993)

Reliability issues of flash memory cells - Seiichi Aritome; Riichiro Shirota; Gertjan Hemink; Tetsuo Endoh; Fujio Masuoka (Proc. IEEE, 1993)

A high-density NAND EEPROM with block-page programming for microcomputer applications - Yoshihisa Iwata; Masaki Momodomi; Tomoharu Tanaka; Hideko Oodaira; Yasuo Itoh; Ryozo Nakayama; Ryouhei Kirisawa; Seiichi Aritome; Tetsuo Endoh; Riichiro Shirota; Kazunori Ohuchi; Fujio Masuoka (IEEE J. Solid State Circuits, 1990)

An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell - Masaki Momodomi; Yasuo Itoh; Riichiro Shirota; Yoshihisa Iwata; Ryozo Nakayama; Ryouhei Kirisawa; Tomoharu Tanaka; Seiichi Aritome; Tetsuo Endoh; Kazunori Ohuchi; Fujjo Masuoka (IEEE J. Solid State Circuits, 1989)