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Chengbo Xue
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2020 – today
- 2024
- [j5]Zhuo Xuan
, Shiwei Ren
A Hardware Acceleration of Maximum Likelihood Estimation Algorithm With Alternating Projection on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 32(6): 1072-1085 (2024) - 2022
- [j4]Zeying Li
Hardware Acceleration of MUSIC Algorithm for Sparse Arrays and Uniform Linear Arrays. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2941-2954 (2022) - [j3]Rongkun Jiang
Deep Learning-Aided Signal Detection for Two-Stage Index Modulated Universal Filtered Multi-Carrier Systems. IEEE Trans. Cogn. Commun. Netw. 8(1): 136-154 (2022) - 2021
- [j2]Yarong Ding, Shiwei Ren
DOA estimation based on sum-difference coarray with virtual array interpolation concept. EURASIP J. Adv. Signal Process. 2021(1): 66 (2021) - 2020
- [j1]Shan Cao
SimuNN: A Pre-RTL Inference, Simulation and Evaluation Framework for Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(2): 217-230 (2020)
2010 – 2019
- 2019
- [c5]Shan Cao, Zhenyi Bao, Chengbo Xue, Wei Deng, Shugong Xu
A Pre-RTL Simulator for Neural Networks. ISCAS 2019: 1-5 - 2018
- [c4]Jiakun Li, Zhe Li, Chengbo Xue, Jingqi Zhang
A Fast Modular Inversion FPGA Implementation over GF(2m) using Modified x2n Unit. ISCAS 2018: 1-5 - [c3]Chengbo Xue, Shan Cao, Rongkun Jiang, Hao Yang:
A Reconfigurable Pipelined Architecture for Convolutional Neural Network Acceleration. ISCAS 2018: 1-5 - 2017
- [c2]Rongkun Jiang, Shan Cao, Chengbo Xue, Lixing Tang:
Modeling and analyzing of underwater acoustic channels with curvilinear boundaries in shallow ocean. ICSPCC 2017: 1-6 - [c1]Lei Zhang, Jianxun Yang
A two-stage variation-aware task mapping scheme for fault-tolerant multi-core Network-on-Chips. ISCAS 2017: 1-4
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