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Hidehiro Toyoda
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2010 – 2019
- 2015
- [c8]Jun Sugawa, Koji Wakayama, Hidehiro Toyoda:
Adaptive FEC control in downstream collaborating with traffic control in OLT for WDM/TDM-PON. ECOC 2015: 1-3 - [c7]Jun Sugawa, Koji Wakayama, Hidehiro Toyoda:
Simultaneous multi-ONU wavelength switching method for coexistence of different λ-tuning times in WDM/TDM-PON. OFC 2015: 1-3 - 2014
- [j6]Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura:
A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion. IEEE J. Solid State Circuits 49(2): 471-485 (2014) - [c6]Jun Sugawa, Toshiyuki Odaka, Hidehiro Toyoda:
Wavelength switching method combined with downstream queue monitoring per ONU for λ-tunable WDM/TDM-PON. ECOC 2014: 1-3 - 2012
- [j5]Masashi Kono, Akihiro Kambe, Hidehiro Toyoda, Shinji Nishimura:
A Novel 400-Gb/s (100-Gb/s×4) Physical-Layer Architecture Using Low-Power Technology. IEICE Trans. Commun. 95-B(11): 3437-3444 (2012) - [c5]Takashi Takemoto, Hiroki Yamashita, Takehito Kamimura, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Kenji Kogo, Yong Lee, Shinji Tsuji, Shinji Nishimura:
A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS. VLSIC 2012: 106-107 - 2011
- [j4]Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura:
A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link. IEEE J. Solid State Circuits 46(12): 3101-3112 (2011) - [c4]Masashi Kono, Akihiro Kambe, Hidehiro Toyoda:
A 400-Gb/s and Low-Power Physical-Layer Architecture for Next-Generation Ethernet. ICC 2011: 1-6 - [c3]Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Akihiro Kambe, Tatsuya Saito, Shinji Nishimura:
10: 4 MUX and 4: 10 DEMUX gearbox LSI for 100-gigabit Ethernet link. ISSCC 2011: 148-150 - 2010
- [j3]Hidehiro Toyoda, Goichi Ono, Shinji Nishimura:
100GbE PHY and MAC layer implementations. IEEE Commun. Mag. 48(3) (2010)
2000 – 2009
- 2008
- [c2]Hidehiro Toyoda, Michitaka Okuno, Shinji Nishimura, Matsuaki Terada:
A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane Ethernet. ICC 2008: 5417-5421 - 2007
- [j2]Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Matsuaki Terada:
A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications. IEICE Trans. Electron. 90-C(10): 1957-1963 (2007) - 2006
- [j1]Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Kouji Fukuda, Kouji Nakahara, Hiroaki Nishi
:
100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet. IEICE Trans. Commun. 89-B(3): 696-703 (2006) - 2005
- [c1]Hidehiro Toyoda, Shinji Nishimura, Michitaka Okuno, Ryouji Yamaoka, Hiroaki Nishi:
A 100-Gb-Ethernet subsystem for next-generation metro-area network. ICC 2005: 1036-1042
Coauthor Index
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