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Miguel Gandara
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2020 – today
- 2023
- [c6]Henry Park, Mohammed Abdullatif, Ehung Chen, Ahmed Elmallah, Qaiser Nehal, Miguel Gandara, Tsz-Bin Liu, Amr Khashaba, Joonyeong Lee, Chih-Yi Kuan, Dhinessh Ramachandran, Ruey-Bo Sun, Atharav Atharav, Yusang Chun, Mantian Zhang, Deng-Fu Weng, Chung-Hsien Tsai, Chen-Hao Chang, Chia-Sheng Peng, Sheng-Tsung Hsu, Tamer A. Ali:
A 4.63pJ/b 112Gb/s DSP-Based PAM-4 Transceiver for a Large-Scale Switch in 5nm FinFET. ISSCC 2023: 110-111 - 2022
- [j3]Ahmet Faruk Budak, Miguel Gandara, Wei Shi, David Z. Pan
, Nan Sun
An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1209-1221 (2022) - 2021
- [j2]Abhishek Mukherjee
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS. IEEE J. Solid State Circuits 56(2): 476-487 (2021) - [c5]Tamer A. Ali, Mohammed Abdullatif, Henry Park, Ehung Chen, Ramy Awad, Miguel Gandara:
56/112Gbps Wireline Transceivers for Next Generation Data Centers on 7nm FINFET CMOS Technology. CICC 2021: 1-6 - 2020
- [c4]Tamer A. Ali, Ehung Chen, Henry Park, Ramy Yousry, Yu-Ming Ying, Mohammed Abdullatif, Miguel Gandara, Chun-Cheng Liu, Po-Shuan Weng, Huan-Sheng Chen, Mohammad Elbadry, Qaiser Nehal, Kun-Hung Tsai, Kevin Tan, Yi-Chieh Huang, Chung-Hsien Tsai, Yuyun Chang, Yuan-Hao Tung:
6.2 A 460mW 112Gb/s DSP-Based Transceiver with 38dB Loss Compensation for Next-Generation Data Centers in 7nm FinFET Technology. ISSCC 2020: 118-120
2010 – 2019
- 2018
- [j1]Shaolan Li
A 13-ENOB Second-Order Noise-Shaping SAR ADC Realizing Optimized NTF Zeros Using the Error-Feedback Structure. IEEE J. Solid State Circuits 53(12): 3484-3496 (2018) - [c3]Shaolan Li, Bo Qiao, Miguel Gandara, Nan Sun:
A 13-ENOB 2nd-order noise-shaping SAR ADC realizing optimized NTF zeros using an error-feedback structure. ISSCC 2018: 234-236 - 2017
- [c2]Miguel Gandara, Paridhi Gulati, Nan Sun:
A 172dB-FoM pipelined SAR ADC using a regenerative amplifier with self-timed gain control and mixed-signal background calibration. A-SSCC 2017: 297-300 - [c1]Miguel Gandara, Wenjuan Guo, Xiyuan Tang, Long Chen, Yeonam Yoon, Nan Sun:
A pipelined SAR ADC reusing the comparator as residue amplifier. CICC 2017: 1-4
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