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Jinsu Jeong
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2020 – today
- 2024
- [j9]Seunghwan Lee
, Seungjoon Eom
Multi-Task Learning for Real-Time BSIM-CMG Parameter Extraction of NSFETs With Multiple Structural Variations. IEEE Access 12: 184619-184628 (2024) - [j8]Seungjoon Eom, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Seunghwan Lee, Jinsu Jeong, Rock-Hyun Baek
Neural Compact Modeling Framework for Flexible Model Parameter Selection with High Accuracy and Fast SPICE Simulation. Adv. Intell. Syst. 6(4) (2024) - 2022
- [j7]Jun-Sik Yoon
DC Performance Variations by Grain Boundary in Source/Drain Epitaxy of Sub-3-nm Nanosheet Field-Effect Transistors. IEEE Access 10: 22032-22037 (2022) - 2021
- [j6]Jinsu Jeong
Analysis of TSV-Induced Mechanical Stress and Electrical Noise Coupling in Sub 5-nm Node Nanosheet FETs for Heterogeneous 3D-ICs. IEEE Access 9: 16728-16735 (2021) - [j5]Junjong Lee
Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes. IEEE Access 9: 138192-138199 (2021) - 2020
- [j4]Jinsu Jeong
Comprehensive Analysis of Source and Drain Recess Depth Variations on Silicon Nanosheet FETs for Sub 5-nm Node SoC Application. IEEE Access 8: 35873-35881 (2020)
2010 – 2019
- 2019
- [j3]Jun-Sik Yoon
Punch-Through-Stopper Free Nanosheet FETs With Crescent Inner-Spacer and Isolated Source/Drain. IEEE Access 7: 38593-38596 (2019) - [j2]Jun-Sik Yoon
Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node. IEEE Access 7: 75762-75767 (2019) - [j1]Jun-Sik Yoon
Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node. IEEE Access 7: 172290-172295 (2019)
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