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BibTeX records: Naifeng Jing
@article{DBLP:journals/mj/LiJJSMW26,
author = {Ang Li and
Jianfei Jiang and
Naifeng Jing and
Yanan Sun and
Zhigang Mao and
Qin Wang},
title = {Signal integrity-aware multi-path design workflow for ultra-large-scale
three-dimensional chips: {A} logic-on-memory stacking case study},
journal = {Microelectron. J.},
volume = {173},
pages = {107171},
year = {2026},
url = {https://doi.org/10.1016/j.mejo.2026.107171},
doi = {10.1016/J.MEJO.2026.107171},
timestamp = {Thu, 21 May 2026 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/LiJJSMW26.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuCYLJWMJ26,
author = {Pengyu Liu and
Liyan Chen and
Zelong Yuan and
Yingkun Liu and
Jianfei Jiang and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
title = {Leveraging Tensor Dataflow for Improved Thermal Performance on 3D-Stacked
{SRAM} Architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {45},
number = {4},
pages = {1598--1610},
year = {2026},
url = {https://doi.org/10.1109/TCAD.2025.3607137},
doi = {10.1109/TCAD.2025.3607137},
timestamp = {Thu, 02 Apr 2026 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuCYLJWMJ26.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YangLGJJWMS26,
author = {Weidong Yang and
Xinmo Li and
Xiangmin Guo and
Jianfei Jiang and
Naifeng Jing and
Qin Wang and
Zhigang Mao and
Weiguang Sheng},
title = {Viper: An ILP-Based Vectorization Framework for Fully Homomorphic
Encryption},
booktitle = {31st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2026, Lantau, Hong Kong, January 19-22, 2026},
pages = {1350--1356},
publisher = {{IEEE}},
year = {2026},
url = {https://doi.org/10.1109/ASP-DAC66049.2026.11420771},
doi = {10.1109/ASP-DAC66049.2026.11420771},
timestamp = {Sat, 28 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/YangLGJJWMS26.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asplos/HeJ0LS26,
author = {Houshu He and
Naifeng Jing and
Li Jiang and
Xiaoyao Liang and
Zhuoran Song},
editor = {Benjamin C. Lee and
Harry Xu and
Mark Silberstein and
Bingyao Li},
title = {{AGS:} Accelerating 3D Gaussian Splatting {SLAM} via CODEC-Assisted
Frame Covisibility Detection},
booktitle = {Proceedings of the 31st {ACM} International Conference on Architectural
Support for Programming Languages and Operating Systems, Volume 1,
{ASPLOS} 2026, Pittsburgh, PA, USA, March 22-26, 2026},
pages = {20--34},
publisher = {{ACM}},
year = {2026},
url = {https://doi.org/10.1145/3760250.3762229},
doi = {10.1145/3760250.3762229},
timestamp = {Tue, 24 Mar 2026 08:36:36 +0100},
biburl = {https://dblp.org/rec/conf/asplos/HeJ0LS26.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/DongYLLLZHHWSMJJ26,
author = {Zizheng Dong and
Chen Yin and
Pengyu Liu and
Shuaipeng Li and
Ang Li and
Weijia Zhu and
Weifeng He and
Guanghui He and
Qin Wang and
Yanan Sun and
Zhigang Mao and
Naifeng Jing and
Jianfei Jiang},
title = {A 51.19 mm\({}^{\mbox{2}}\), 4 TB/s bandwidth 3D Logic-on-SRAM Stacking
{CGRA} Chip},
booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2026, Seattle,
WA, USA, April 19-23, 2026},
pages = {1--5},
publisher = {{IEEE}},
year = {2026},
url = {https://doi.org/10.1109/CICC65509.2026.11509617},
doi = {10.1109/CICC65509.2026.11509617},
timestamp = {Mon, 08 Jun 2026 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/DongYLLLZHHWSMJJ26.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/LiLLDGSJWHJ25,
author = {Kunyue Li and
Shuaipeng Li and
Xiaoyan Li and
Zizheng Dong and
Sai Gao and
Jialei Sun and
Naifeng Jing and
Qin Wang and
Guanghui He and
Jianfei Jiang},
title = {Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization
in a Chiplet-Based System},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {15},
number = {4},
pages = {599--608},
year = {2025},
url = {https://doi.org/10.1109/JETCAS.2025.3590822},
doi = {10.1109/JETCAS.2025.3590822},
timestamp = {Sat, 17 Jan 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/esticas/LiLLDGSJWHJ25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/SongLJJL25,
author = {Zhuoran Song and
Jiabei Long and
Li Jiang and
Naifeng Jing and
Xiaoyao Liang},
title = {GCNTrain+: {A} Versatile and Efficient Accelerator for Graph Convolutional
Neural Network Training},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {22},
number = {1},
pages = {22:1--22:22},
year = {2025},
url = {https://doi.org/10.1145/3705317},
doi = {10.1145/3705317},
timestamp = {Wed, 11 Jun 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/SongLJJL25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/WangSQLJJL25,
author = {Xuhang Wang and
Zhuoran Song and
Chunyu Qi and
Fangxin Liu and
Naifeng Jing and
Li Jiang and
Xiaoyao Liang},
title = {{RTSA:} {A} Run-Through Sparse Attention Framework for Video Transformer},
journal = {{IEEE} Trans. Computers},
volume = {74},
number = {6},
pages = {1949--1962},
year = {2025},
url = {https://doi.org/10.1109/TC.2025.3547139},
doi = {10.1109/TC.2025.3547139},
timestamp = {Wed, 11 Jun 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/WangSQLJJL25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenLLJWMJ25,
author = {Liyan Chen and
Pengyu Liu and
Dongxu Lyu and
Jianfei Jiang and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
title = {Bridge-NDP: Efficient Communication-Computation Overlap in Near Data
Processing System},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {44},
number = {8},
pages = {2939--2951},
year = {2025},
url = {https://doi.org/10.1109/TCAD.2025.3531254},
doi = {10.1109/TCAD.2025.3531254},
timestamp = {Sat, 09 Aug 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenLLJWMJ25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiYJJJMW25,
author = {Shuya Ji and
Weidong Yang and
Jianfei Jiang and
Naifeng Jing and
Honglan Jiang and
Zhigang Mao and
Qin Wang},
title = {{MACS:} {A} Multidomain Collaborative Adaptive Clock Scheme for Large-Scale
Reconfigurable Dataflow Accelerators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {44},
number = {8},
pages = {2992--3005},
year = {2025},
url = {https://doi.org/10.1109/TCAD.2025.3533305},
doi = {10.1109/TCAD.2025.3533305},
timestamp = {Sat, 09 Aug 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiYJJJMW25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DongLZLWJSJM25,
author = {Zizheng Dong and
Shuaipeng Li and
Weijia Zhu and
Ang Li and
Qin Wang and
Naifeng Jing and
Weiguang Sheng and
Jianfei Jiang and
Zhigang Mao},
title = {A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory
{CGRA} Chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {33},
number = {6},
pages = {1502--1515},
year = {2025},
url = {https://doi.org/10.1109/TVLSI.2025.3538883},
doi = {10.1109/TVLSI.2025.3538883},
timestamp = {Thu, 07 May 2026 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/DongLZLWJSJM25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/appt/ZhaoLGLTGYJJ25,
author = {Yilong Zhao and
Fangxin Liu and
Mingyu Gao and
Xiaoyao Liang and
Qidong Tang and
Chengyang Gu and
Tao Yang and
Naifeng Jing and
Li Jiang},
editor = {Chao Li and
Xuehai Qian and
Dimitris Gizopoulos and
Boris Grot},
title = {{STAMP:} Accelerating Second-Order {DNN} Training Via ReRAM-Based
Processing-in-Memory Architecture},
booktitle = {Advanced Parallel Processing Technologies - 16th International Symposium,
{APPT} 2025, Athens, Greece, July 13-16, 2025, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {16062},
pages = {160--170},
publisher = {Springer},
year = {2025},
url = {https://doi.org/10.1007/978-981-95-1021-4\_12},
doi = {10.1007/978-981-95-1021-4\_12},
timestamp = {Fri, 13 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/appt/ZhaoLGLTGYJJ25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Chen00MJ25,
author = {Liyan Chen and
Jianfei Jiang and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
editor = {Yuichi Nakamura and
Yu Wang},
title = {{MDNMP:} Metapath-Driven Software-Hardware Co-Design for {HGNN} Acceleration
with Near-Memory Processing},
booktitle = {Proceedings of the 30th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2025, Tokyo, Japan, January 20-23, 2025},
pages = {656--662},
publisher = {{ACM}},
year = {2025},
url = {https://doi.org/10.1145/3658617.3697578},
doi = {10.1145/3658617.3697578},
timestamp = {Fri, 07 Mar 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/Chen00MJ25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChenLLJWMJ25,
author = {Liyan Chen and
Dongxu Lyu and
Zhenyu Li and
Jianfei Jiang and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
title = {AttenPIM: Accelerating {LLM} Attention with Dual-mode {GEMV} in Processing-in-Memory},
booktitle = {62nd {ACM/IEEE} Design Automation Conference, {DAC} 2025, San Francisco,
CA, USA, June 22-25, 2025},
pages = {1--7},
publisher = {{IEEE}},
year = {2025},
url = {https://doi.org/10.1109/DAC63849.2025.11133230},
doi = {10.1109/DAC63849.2025.11133230},
timestamp = {Mon, 22 Sep 2025 21:08:54 +0200},
biburl = {https://dblp.org/rec/conf/dac/ChenLLJWMJ25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/QiWCYJZWFLS25,
author = {Chunyu Qi and
Xuhang Wang and
Ruiyang Chen and
Yuanzheng Yao and
Naifeng Jing and
Chen Zhang and
Jun Wang and
Zhihui Fu and
Xiaoyao Liang and
Zhuoran Song},
title = {MHDiff: Memory- and Hardware-Efficient Diffusion Acceleration via
Focal Pixel Aware Quantization},
booktitle = {62nd {ACM/IEEE} Design Automation Conference, {DAC} 2025, San Francisco,
CA, USA, June 22-25, 2025},
pages = {1--7},
publisher = {{IEEE}},
year = {2025},
url = {https://doi.org/10.1109/DAC63849.2025.11133171},
doi = {10.1109/DAC63849.2025.11133171},
timestamp = {Thu, 26 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/QiWCYJZWFLS25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/XuYYSJWJ25,
author = {Lei Xu and
Chen Yin and
Zelong Yuan and
Weiguang Sheng and
Jianfei Jiang and
Qin Wang and
Naifeng Jing},
title = {Principle-based Dataflow Optimization for Communication Lower Bound
in Operator-Fused Tensor Accelerator},
booktitle = {62nd {ACM/IEEE} Design Automation Conference, {DAC} 2025, San Francisco,
CA, USA, June 22-25, 2025},
pages = {1--7},
publisher = {{IEEE}},
year = {2025},
url = {https://doi.org/10.1109/DAC63849.2025.11132765},
doi = {10.1109/DAC63849.2025.11132765},
timestamp = {Mon, 22 Sep 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/XuYYSJWJ25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/YaoZQCWFJLS25,
author = {Yuanzheng Yao and
Chen Zhang and
Chunyu Qi and
Ruiyang Chen and
Jun Wang and
Zhihui Fu and
Naifeng Jing and
Xiaoyao Liang and
Zhuoran Song},
title = {SynGPU: Synergizing {CUDA} and Bit-Serial Tensor Cores for Vision
Transformer Acceleration on {GPU}},
booktitle = {62nd {ACM/IEEE} Design Automation Conference, {DAC} 2025, San Francisco,
CA, USA, June 22-25, 2025},
pages = {1--7},
publisher = {{IEEE}},
year = {2025},
url = {https://doi.org/10.1109/DAC63849.2025.11132753},
doi = {10.1109/DAC63849.2025.11132753},
timestamp = {Thu, 26 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/YaoZQCWFJLS25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/YangJ0JWMS25,
author = {Weidong Yang and
Shuya Ji and
Jianfei Jiang and
Naifeng Jing and
Qin Wang and
Zhigang Mao and
Weiguang Sheng},
title = {{HEILP:} An ILP-Based Scale Management Method for Homomorphic Encryption
Compiler},
booktitle = {Design, Automation {\&} Test in Europe Conference, {DATE} 2025,
Lyon, France, March 31 - April 2, 2025},
pages = {1--6},
publisher = {{IEEE}},
year = {2025},
url = {https://doi.org/10.23919/DATE64628.2025.10992881},
doi = {10.23919/DATE64628.2025.10992881},
timestamp = {Tue, 05 Aug 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/YangJ0JWMS25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/ChenL00MJ25,
author = {Liyan Chen and
Dongxu Lyu and
Jianfei Jiang and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
title = {AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory
Processing},
booktitle = {{IEEE} International Symposium on High Performance Computer Architecture,
{HPCA} 2025, Las Vegas, NV, USA, March 1-5, 2025},
pages = {518--532},
publisher = {{IEEE}},
year = {2025},
url = {https://doi.org/10.1109/HPCA61900.2025.00047},
doi = {10.1109/HPCA61900.2025.00047},
timestamp = {Sat, 31 May 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/hpca/ChenL00MJ25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/ChenYGQWJJW25,
author = {Wanqi Chen and
Weidong Yang and
Yiming Guo and
Jing Qiu and
Renpei Wang and
Jianfei Jiang and
Naifeng Jing and
Qin Wang},
title = {{RVME:} An Efficient Matrix Engine Design Based on Matrix Extension
of {RISC-V}},
booktitle = {43rd {IEEE} International Conference on Computer Design, {ICCD} 2025,
Richardson, TX, USA, November 10-12, 2025},
pages = {1--8},
publisher = {{IEEE}},
year = {2025},
url = {https://doi.org/10.1109/ICCD65941.2025.00092},
doi = {10.1109/ICCD65941.2025.00092},
timestamp = {Sun, 01 Feb 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/ChenYGQWJJW25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/MoWW0CMJCX0025,
author = {Zhiwen Mo and
Lei Wang and
Jianyu Wei and
Zhichen Zeng and
Shijie Cao and
Lingxiao Ma and
Naifeng Jing and
Ting Cao and
Jilong Xue and
Fan Yang and
Mao Yang},
title = {{LUT} Tensor Core: {A} Software-Hardware Co-Design for LUT-Based Low-Bit
{LLM} Inference},
booktitle = {Proceedings of the 52nd Annual International Symposium on Computer
Architecture, {ISCA} 2025, Tokyo, Japan, June 21-25, 2025},
pages = {514--528},
publisher = {{ACM}},
year = {2025},
url = {https://doi.org/10.1145/3695053.3731057},
doi = {10.1145/3695053.3731057},
timestamp = {Mon, 08 Dec 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/MoWW0CMJCX0025.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/ChenSZZ0JLG25,
author = {Ruiyang Chen and
Zhuoran Song and
Yicheng Zheng and
Zeyu Zhu and
Gang Li and
Naifeng Jing and
Xiaoyao Liang and
Haibing Guan},
title = {{HEAT:} {NPU-NDP} HEterogeneous Architecture for Transformer-Empowered
Graph Neural Networks},
booktitle = {Proceedings of the 58th {IEEE/ACM} International Symposium on Microarchitecture,
{MICRO} 2025, Seoul, Republic of Korea, October 18-22, 2025},
pages = {263--276},
publisher = {{ACM}},
year = {2025},
url = {https://doi.org/10.1145/3725843.3756117},
doi = {10.1145/3725843.3756117},
timestamp = {Thu, 05 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/ChenSZZ0JLG25.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2504-17584,
author = {Qingyuan Liu and
Liyan Chen and
Yanning Yang and
Haocheng Wang and
Dong Du and
Zhigang Mao and
Naifeng Jing and
Yubin Xia and
Haibo Chen},
title = {{L3:} {DIMM-PIM} Integrated Architecture and Coordination for Scalable
Long-Context {LLM} Inference},
journal = {CoRR},
volume = {abs/2504.17584},
year = {2025},
url = {https://doi.org/10.48550/arXiv.2504.17584},
doi = {10.48550/ARXIV.2504.17584},
eprinttype = {arXiv},
eprint = {2504.17584},
timestamp = {Fri, 23 May 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2504-17584.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2509-00433,
author = {Houshu He and
Naifeng Jing and
Li Jiang and
Xiaoyao Liang and
Zhuoran Song},
title = {{AGS:} Accelerating 3D Gaussian Splatting {SLAM} via CODEC-Assisted
Frame Covisibility Detection},
journal = {CoRR},
volume = {abs/2509.00433},
year = {2025},
url = {https://doi.org/10.48550/arXiv.2509.00433},
doi = {10.48550/ARXIV.2509.00433},
eprinttype = {arXiv},
eprint = {2509.00433},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2509-00433.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/eswa/LiZCWJMJ24,
author = {Kunyue Li and
Zhengji Zhao and
Qixuan Cai and
Qin Wang and
Naifeng Jing and
Zhigang Mao and
Jianfei Jiang},
title = {A novel vehicle collision detection system: Integrating audio-visual
fusion for enhanced performance},
journal = {Expert Syst. Appl.},
volume = {249},
pages = {123828},
year = {2024},
url = {https://doi.org/10.1016/j.eswa.2024.123828},
doi = {10.1016/J.ESWA.2024.123828},
timestamp = {Fri, 31 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/eswa/LiZCWJMJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/SongYSHJJL24,
author = {Zhuoran Song and
Zhongkai Yu and
Xinkai Song and
Yifan Hao and
Li Jiang and
Naifeng Jing and
Xiaoyao Liang},
title = {Environmental Condition Aware Super-Resolution Acceleration Framework
in Server-Client Hierarchies},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {21},
number = {4},
pages = {65:1--65:26},
year = {2024},
url = {https://doi.org/10.1145/3678008},
doi = {10.1145/3678008},
timestamp = {Wed, 14 May 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/SongYSHJJL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangJWMJ24,
author = {Zihan Zhang and
Jianfei Jiang and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
title = {3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based {CNN} Accelerator},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {1},
pages = {176--188},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2023.3297968},
doi = {10.1109/TCAD.2023.3297968},
timestamp = {Sat, 13 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhangJWMJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YinJWMJ24,
author = {Chen Yin and
Jianfei Jiang and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
title = {DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With
Delta Updating},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {4},
pages = {1163--1176},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2023.3335153},
doi = {10.1109/TCAD.2023.3335153},
timestamp = {Mon, 01 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YinJWMJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangYJJJWMS24,
author = {Weidong Yang and
Yuqing Yang and
Shuya Ji and
Jianfei Jiang and
Naifeng Jing and
Qin Wang and
Zhigang Mao and
Weiguang Sheng},
title = {RecPIM: Efficient In-Memory Processing for Personalized Recommendation
Inference Using Near-Bank Architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {10},
pages = {2854--2867},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2024.3386117},
doi = {10.1109/TCAD.2024.3386117},
timestamp = {Tue, 22 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangYJJJWMS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuLCJWMJ24,
author = {Pengyu Liu and
Ang Li and
Liyan Chen and
Jianfei Jiang and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
title = {A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined
Execution in Spatial Programmable Architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {12},
pages = {4640--4652},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2024.3409653},
doi = {10.1109/TCAD.2024.3409653},
timestamp = {Wed, 08 Oct 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuLCJWMJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiSALLZWLLJL24,
author = {Xing Li and
Zhuoran Song and
Rachata Ausavarungnirun and
Xiao Liu and
Xueyuan Liu and
Xuan Zhang and
Xuhang Wang and
Jiayao Ling and
Gang Li and
Naifeng Jing and
Xiaoyao Liang},
title = {Janus: {A} Flexible Processing-in-Memory Graph Accelerator Toward
Sparsity},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {43},
number = {12},
pages = {4813--4826},
year = {2024},
url = {https://doi.org/10.1109/TCAD.2024.3405395},
doi = {10.1109/TCAD.2024.3405395},
timestamp = {Mon, 13 Oct 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiSALLZWLLJL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Yin00MJ24,
author = {Chen Yin and
Jianfei Jiang and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
title = {SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph
Neural Network Acceleration},
booktitle = {Proceedings of the 29th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2024, Incheon, Korea, January 22-25, 2024},
pages = {225--230},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ASP-DAC58780.2024.10473883},
doi = {10.1109/ASP-DAC58780.2024.10473883},
timestamp = {Thu, 22 Aug 2024 15:31:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/Yin00MJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Chen00MJ24,
author = {Liyan Chen and
Jianfei Jiang and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
title = {Bridge-NDP: Achieving Efficient Communication-Computation Overlap
in Near Data Processing with Bridge Architecture},
booktitle = {Proceedings of the 29th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2024, Incheon, Korea, January 22-25, 2024},
pages = {460--465},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ASP-DAC58780.2024.10473860},
doi = {10.1109/ASP-DAC58780.2024.10473860},
timestamp = {Sat, 31 May 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/Chen00MJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asplos/SongQLJL24,
author = {Zhuoran Song and
Chunyu Qi and
Fangxin Liu and
Naifeng Jing and
Xiaoyao Liang},
editor = {Rajiv Gupta and
Nael B. Abu{-}Ghazaleh and
Madan Musuvathi and
Dan Tsafrir},
title = {{CMC:} Video Transformer Acceleration via {CODEC} Assisted Matrix
Condensing},
booktitle = {Proceedings of the 29th {ACM} International Conference on Architectural
Support for Programming Languages and Operating Systems, Volume 2,
{ASPLOS} 2024, La Jolla, CA, USA, 27 April 2024- 1 May 2024},
pages = {201--215},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3620665.3640393},
doi = {10.1145/3620665.3640393},
timestamp = {Sat, 04 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asplos/SongQLJL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/XuM00J24,
author = {Lei Xu and
Zhiwen Mo and
Qin Wang and
Jianfei Jiang and
Naifeng Jing},
editor = {Vivek De},
title = {Enabling Multiple Tensor-wise Operator Fusion for Transformer Models
on Spatial Accelerators},
booktitle = {Proceedings of the 61st {ACM/IEEE} Design Automation Conference, {DAC}
2024, San Francisco, CA, USA, June 23-27, 2024},
pages = {232:1--232:6},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3649329.3657317},
doi = {10.1145/3649329.3657317},
timestamp = {Sat, 30 Nov 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/XuM00J24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/europar/ZhangSLHJJL24,
author = {Xuan Zhang and
Zhuoran Song and
Xing Li and
Zhezhi He and
Naifeng Jing and
Li Jiang and
Xiaoyao Liang},
editor = {Jes{\'{u}}s Carretero and
Sameer Shende and
Javier Garc{\'{\i}}a{-}Blas and
Ivona Brandic and
Katzalin Olcoz and
Martin Schreiber},
title = {Watt: {A} Write-Optimized RRAM-Based Accelerator for Attention},
booktitle = {Euro-Par 2024: Parallel Processing - 30th European Conference on Parallel
and Distributed Processing, Madrid, Spain, August 26-30, 2024, Proceedings,
Part {II}},
series = {Lecture Notes in Computer Science},
volume = {14802},
pages = {107--120},
publisher = {Springer},
year = {2024},
url = {https://doi.org/10.1007/978-3-031-69766-1\_8},
doi = {10.1007/978-3-031-69766-1\_8},
timestamp = {Tue, 14 Oct 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/europar/ZhangSLHJJL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/YuLJ0S024,
author = {Duo Yu and
Ang Li and
Naifeng Jing and
Jianfei Jiang and
Weiguang Sheng and
Qin Wang},
editor = {Inna Partin{-}Vaisband and
Srinivas Katkoori and
Lu Peng and
Boris Vaisband and
Tooraj Nikoubin},
title = {{VDA:} {A} Simple but Efficient Virtual-Channel-Based Deadlock Avoidance
Scheme for Scalable Chiplet Networks},
booktitle = {Proceedings of the Great Lakes Symposium on {VLSI} 2024, {GLSVLSI}
2024, Clearwater, FL, USA, June 12-14, 2024},
pages = {357--363},
publisher = {{ACM}},
year = {2024},
url = {https://doi.org/10.1145/3649476.3658704},
doi = {10.1145/3649476.3658704},
timestamp = {Wed, 08 Oct 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/YuLJ0S024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/ZhangSZLLLH0JL24,
author = {Xuan Zhang and
Zhuoran Song and
Peng Zhou and
Xing Li and
Xueyuan Liu and
Xiaolong Lin and
Zhezhi He and
Li Jiang and
Naifeng Jing and
Xiaoyao Liang},
title = {Early: An Importance-Aware Early Firing and Exit for {SNN} Acceleration},
booktitle = {42nd {IEEE} International Conference on Computer Design, {ICCD} 2024,
Milan, Italy, November 18-20, 2024},
pages = {624--627},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ICCD63220.2024.00100},
doi = {10.1109/ICCD63220.2024.00100},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/ZhangSZLLLH0JL24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/ZhaoGLHWLLXDYJLJ24,
author = {Yilong Zhao and
Mingyu Gao and
Fangxin Liu and
Yiwei Hu and
Zongwu Wang and
Han Lin and
Jin Li and
He Xian and
Hanlin Dong and
Tao Yang and
Naifeng Jing and
Xiaoyao Liang and
Li Jiang},
title = {{UM-PIM:} DRAM-based {PIM} with Uniform {\&} Shared Memory Space},
booktitle = {51st {ACM/IEEE} Annual International Symposium on Computer Architecture,
{ISCA} 2024, Buenos Aires, Argentina, June 29 - July 3, 2024},
pages = {644--659},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISCA59077.2024.00053},
doi = {10.1109/ISCA59077.2024.00053},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/ZhaoGLHWLLXDYJLJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/XieDSGLJ0024,
author = {Lin Xie and
Zizheng Dong and
Jialei Sun and
Sai Gao and
Shuaipeng Li and
Naifeng Jing and
Qin Wang and
Jianfei Jiang},
title = {A 0.8-ps {RMS} Precision Period Jitter Measurement Circuit with Offset
Reduction},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2024,
Singapore, May 19-22, 2024},
pages = {1--5},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISCAS58744.2024.10557978},
doi = {10.1109/ISCAS58744.2024.10557978},
timestamp = {Sat, 15 Nov 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/XieDSGLJ0024.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/YuanYLYXSJ24,
author = {Zelong Yuan and
Siwei Yuan and
Pengyu Liu and
Chen Yin and
Lei Xu and
Weiguang Sheng and
Naifeng Jing},
title = {A Flexible and High-Precision Activation Function Unit Based on Equi-Error
Partitioning Algorithm},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2024,
Singapore, May 19-22, 2024},
pages = {1--5},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ISCAS58744.2024.10558019},
doi = {10.1109/ISCAS58744.2024.10558019},
timestamp = {Mon, 03 Mar 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/YuanYLYXSJ24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2408-06003,
author = {Zhiwen Mo and
Lei Wang and
Jianyu Wei and
Zhichen Zeng and
Shijie Cao and
Lingxiao Ma and
Naifeng Jing and
Ting Cao and
Jilong Xue and
Fan Yang and
Mao Yang},
title = {{LUT} Tensor Core: Lookup Table Enables Efficient Low-Bit {LLM} Inference
Acceleration},
journal = {CoRR},
volume = {abs/2408.06003},
year = {2024},
url = {https://doi.org/10.48550/arXiv.2408.06003},
doi = {10.48550/ARXIV.2408.06003},
eprinttype = {arXiv},
eprint = {2408.06003},
timestamp = {Tue, 09 Dec 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2408-06003.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JingZSLCWJ23,
author = {Naifeng Jing and
Zihan Zhang and
Yongshuai Sun and
Pengyu Liu and
Liyan Chen and
Qin Wang and
Jianfei Jiang},
title = {Exploiting bit sparsity in both activation and weight in neural networks
accelerators},
journal = {Integr.},
volume = {88},
pages = {400--409},
year = {2023},
url = {https://doi.org/10.1016/j.vlsi.2022.09.008},
doi = {10.1016/J.VLSI.2022.09.008},
timestamp = {Wed, 11 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JingZSLCWJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YinJJWM23,
author = {Chen Yin and
Naifeng Jing and
Jianfei Jiang and
Qin Wang and
Zhigang Mao},
title = {A Reschedulable Dataflow-SIMD Execution for Increased Utilization
in {CGRA} Cross-Domain Acceleration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {3},
pages = {874--886},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3185544},
doi = {10.1109/TCAD.2022.3185544},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/YinJJWM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SongLJJL23,
author = {Zhuoran Song and
Heng Lu and
Li Jiang and
Naifeng Jing and
Xiaoyao Liang},
title = {Real-Time Video Recognition via Decoder-Assisted Neural Network Acceleration
Framework},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {7},
pages = {2238--2251},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3217667},
doi = {10.1109/TCAD.2022.3217667},
timestamp = {Fri, 07 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SongLJJL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SongJL23,
author = {Zhuoran Song and
Naifeng Jing and
Xiaoyao Liang},
title = {E\({}^{\mbox{2}}\)-VOR: An End-to-End En/Decoder Architecture for
Efficient Video Object Recognition},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {28},
number = {1},
pages = {10:1--10:21},
year = {2023},
url = {https://doi.org/10.1145/3543852},
doi = {10.1145/3543852},
timestamp = {Sun, 16 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/SongJL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/SongLYLJL23,
author = {Zhuoran Song and
Wanzhen Liu and
Tao Yang and
Fangxin Liu and
Naifeng Jing and
Xiaoyao Liang},
title = {A Point Cloud Video Recognition Acceleration Framework Based on Tempo-Spatial
Information},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {34},
number = {12},
pages = {3224--3237},
year = {2023},
url = {https://doi.org/10.1109/TPDS.2023.3323263},
doi = {10.1109/TPDS.2023.3323263},
timestamp = {Wed, 16 Apr 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tpds/SongLYLJL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/acmturc/SongJL23,
author = {Zhuoran Song and
Naifeng Jing and
Xiaoyao Liang},
title = {{PRADA:} Point Cloud Recognition Acceleration via Dynamic Approximation},
booktitle = {Proceedings of the {ACM} Turing Award Celebration Conference - China
2023, {ACM} {TURC} 2023, Wuhan, China, July 28-30, 2023},
pages = {49--50},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3603165.3607391},
doi = {10.1145/3603165.3607391},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/acmturc/SongJL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/ChenZJSWJ23,
author = {Zhuo Chen and
Zihan Zhang and
Jianfei Jiang and
Weiguang Sheng and
Qin Wang and
Naifeng Jing},
title = {ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse
ReRAM Accelerator},
booktitle = {15th {IEEE} International Conference on ASIC, {ASICON} 2023, Nanjing,
China, October 24-27, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ASICON58565.2023.10396618},
doi = {10.1109/ASICON58565.2023.10396618},
timestamp = {Fri, 16 Feb 2024 14:02:58 +0100},
biburl = {https://dblp.org/rec/conf/asicon/ChenZJSWJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/GaoLWJJ23,
author = {Jianing Gao and
Lingyi Liu and
Qin Wang and
Naifeng Jing and
Jianfei Jiang},
title = {High-Performance Genomic Analysis Heterogeneous System Using OpenCL},
booktitle = {15th {IEEE} International Conference on ASIC, {ASICON} 2023, Nanjing,
China, October 24-27, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ASICON58565.2023.10396387},
doi = {10.1109/ASICON58565.2023.10396387},
timestamp = {Tue, 11 Jun 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asicon/GaoLWJJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/GaoSDWJJ23,
author = {Jianing Gao and
Qiming Shao and
Fangyu Deng and
Qin Wang and
Naifeng Jing and
Jianfei Jiang},
title = {An NoC-based {CNN} Accelerator for Edge Computing},
booktitle = {15th {IEEE} International Conference on ASIC, {ASICON} 2023, Nanjing,
China, October 24-27, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ASICON58565.2023.10396346},
doi = {10.1109/ASICON58565.2023.10396346},
timestamp = {Fri, 16 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asicon/GaoSDWJJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YangYWJ0MS23,
author = {Yuqing Yang and
Weidong Yang and
Qin Wang and
Naifeng Jing and
Jianfei Jiang and
Zhigang Mao and
Weiguang Sheng},
editor = {Atsushi Takahashi},
title = {An Efficient near-Bank Processing Architecture for Personalized Recommendation
System},
booktitle = {Proceedings of the 28th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2023, Tokyo, Japan, January 16-19, 2023},
pages = {122--127},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3566097.3567857},
doi = {10.1145/3566097.3567857},
timestamp = {Sun, 06 Oct 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/YangYWJ0MS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LinLLLZSJL23,
author = {Xiaolong Lin and
Gang Li and
Zizhao Liu and
Yadong Liu and
Fan Zhang and
Zhuoran Song and
Naifeng Jing and
Xiaoyao Liang},
title = {AdaS: {A} Fast and Energy-Efficient {CNN} Accelerator Exploiting Bit-Sparsity},
booktitle = {60th {ACM/IEEE} Design Automation Conference, {DAC} 2023, San Francisco,
CA, USA, July 9-13, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/DAC56929.2023.10247662},
doi = {10.1109/DAC56929.2023.10247662},
timestamp = {Thu, 01 May 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/LinLLLZSJL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SongLLJJL23,
author = {Zhuoran Song and
Heng Lu and
Gang Li and
Li Jiang and
Naifeng Jing and
Xiaoyao Liang},
title = {{PRADA:} Point Cloud Recognition Acceleration via Dynamic Approximation},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137301},
doi = {10.23919/DATE56975.2023.10137301},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/SongLLJJL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/LiuZYCJWMJ23,
author = {Pengyu Liu and
Zihan Zhang and
Chen Yin and
Liyan Chen and
Jianfei Jiang and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
editor = {Nele Mentens and
Leonel Sousa and
Pedro Trancoso and
Nikela Papadopoulou and
Ioannis Sourdis},
title = {Pipeline Balancing for Integrated Mapping in High Performance Spatial
Programmable Architecture},
booktitle = {33rd International Conference on Field-Programmable Logic and Applications,
{FPL} 2023, Gothenburg, Sweden, September 4-8, 2023},
pages = {116--122},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/FPL60245.2023.00024},
doi = {10.1109/FPL60245.2023.00024},
timestamp = {Wed, 11 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/LiuZYCJWMJ23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/JiY0JSL023,
author = {Shuya Ji and
Weidong Yang and
Jianfei Jiang and
Naifeng Jing and
Weiguang Sheng and
Ang Li and
Qin Wang},
title = {{ACET:} An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack
for Reconfigurable Processors},
booktitle = {41st {IEEE} International Conference on Computer Design, {ICCD} 2023,
Washington, DC, USA, November 6-8, 2023},
pages = {54--61},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCD58817.2023.00018},
doi = {10.1109/ICCD58817.2023.00018},
timestamp = {Wed, 08 Oct 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccd/JiY0JSL023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/ZhangSLH0JL23,
author = {Xuan Zhang and
Zhuoran Song and
Xing Li and
Zhezhi He and
Li Jiang and
Naifeng Jing and
Xiaoyao Liang},
title = {HyAcc: {A} Hybrid {CAM-MAC} RRAM-based Accelerator for Recommendation
Model},
booktitle = {41st {IEEE} International Conference on Computer Design, {ICCD} 2023,
Washington, DC, USA, November 6-8, 2023},
pages = {375--382},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ICCD58817.2023.00063},
doi = {10.1109/ICCD58817.2023.00063},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/ZhangSLH0JL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/prcv/XiangJJGSMW23,
author = {Haifeng Xiang and
Naifeng Jing and
Jianfei Jiang and
Hongbo Guo and
Weiguang Sheng and
Zhigang Mao and
Qin Wang},
editor = {Qingshan Liu and
Hanzi Wang and
Zhanyu Ma and
Weishi Zheng and
Hongbin Zha and
Xilin Chen and
Liang Wang and
Rongrong Ji},
title = {RTMDet-R2: An Improved Real-Time Rotated Object Detector},
booktitle = {Pattern Recognition and Computer Vision - 6th Chinese Conference,
{PRCV} 2023, Xiamen, China, October 13-15, 2023, Proceedings, Part
{XII}},
series = {Lecture Notes in Computer Science},
volume = {14436},
pages = {352--364},
publisher = {Springer},
year = {2023},
url = {https://doi.org/10.1007/978-981-99-8555-5\_28},
doi = {10.1007/978-981-99-8555-5\_28},
timestamp = {Tue, 20 Aug 2024 07:54:44 +0200},
biburl = {https://dblp.org/rec/conf/prcv/XiangJJGSMW23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/lgrs/DengWJHJSM22,
author = {Guochao Deng and
Qin Wang and
Jianfei Jiang and
Qirun Hong and
Naifeng Jing and
Weiguang Sheng and
Zhigang Mao},
title = {A Low Coupling and Lightweight Algorithm for Ship Detection in Optical
Remote Sensing Images},
journal = {{IEEE} Geosci. Remote. Sens. Lett.},
volume = {19},
pages = {1--5},
year = {2022},
url = {https://doi.org/10.1109/LGRS.2022.3188850},
doi = {10.1109/LGRS.2022.3188850},
timestamp = {Mon, 08 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/lgrs/DengWJHJSM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiJMC22,
author = {Taozhong Li and
Naifeng Jing and
Zhigang Mao and
Yiran Chen},
title = {A Hybrid-Grained Remapping Defense Scheme Against Hard Failures for
Row-Column-NVM},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {6},
pages = {1842--1854},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3097288},
doi = {10.1109/TCAD.2021.3097288},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiJMC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Zhang000MJ22,
author = {Zihan Zhang and
Jianfei Jiang and
Yongxin Zhu and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
title = {A Universal RRAM-Based {DNN} Accelerator With Programmable Crossbars
Beyond {MVM} Operator},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {7},
pages = {2094--2106},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3107252},
doi = {10.1109/TCAD.2021.3107252},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Zhang000MJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiJJWMC22,
author = {Taozhong Li and
Naifeng Jing and
Jianfei Jiang and
Qin Wang and
Zhigang Mao and
Yiran Chen},
title = {A Novel Architecture Design for Output Significance Aligned Flow with
Adaptive Control in ReRAM-based Neural Network Accelerator},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {27},
number = {6},
pages = {57:1--57:22},
year = {2022},
url = {https://doi.org/10.1145/3510819},
doi = {10.1145/3510819},
timestamp = {Sun, 19 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LiJJWMC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiWJSJM22,
author = {Shengzhao Li and
Qin Wang and
Jianfei Jiang and
Weiguang Sheng and
Naifeng Jing and
Zhigang Mao},
title = {An Efficient {CNN} Accelerator Using Inter-Frame Data Reuse of Videos
on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {11},
pages = {1587--1600},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3151788},
doi = {10.1109/TVLSI.2022.3151788},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiWJSJM22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GuoZJWJ22,
author = {Mengyu Guo and
Zihan Zhang and
Jianfei Jiang and
Qin Wang and
Naifeng Jing},
title = {Boosting ReRAM-based {DNN} by Row Activation Oversubscription},
booktitle = {27th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2022, Taipei, Taiwan, January 17-20, 2022},
pages = {604--609},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ASP-DAC52403.2022.9712520},
doi = {10.1109/ASP-DAC52403.2022.9712520},
timestamp = {Wed, 22 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/GuoZJWJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SongYJL22,
author = {Zhuoran Song and
Zhongkai Yu and
Naifeng Jing and
Xiaoyao Liang},
editor = {Rob Oshana},
title = {E\({}^{\mbox{2}}\)SR: an end-to-end video {CODEC} assisted system
for super resolution acceleration},
booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco,
California, USA, July 10 - 14, 2022},
pages = {229--234},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3489517.3530423},
doi = {10.1145/3489517.3530423},
timestamp = {Thu, 25 Aug 2022 14:23:32 +0200},
biburl = {https://dblp.org/rec/conf/dac/SongYJL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiuZWCHJLJ22,
author = {Fangxin Liu and
Wenbo Zhao and
Zongwu Wang and
Yongbiao Chen and
Zhezhi He and
Naifeng Jing and
Xiaoyao Liang and
Li Jiang},
editor = {Rob Oshana},
title = {{EBSP:} evolving bit sparsity patterns for hardware-friendly inference
of quantized deep neural networks},
booktitle = {{DAC} '22: 59th {ACM/IEEE} Design Automation Conference, San Francisco,
California, USA, July 10 - 14, 2022},
pages = {259--264},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3489517.3530660},
doi = {10.1145/3489517.3530660},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiuZWCHJLJ22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LiALLZLSJL22,
author = {Xing Li and
Rachata Ausavarungnirun and
Xiao Liu and
Xueyuan Liu and
Xuan Zhang and
Heng Lu and
Zhuoran Song and
Naifeng Jing and
Xiaoyao Liang},
editor = {Tulika Mitra and
Evangeline F. Y. Young and
Jinjun Xiong},
title = {Gzippo: Highly-Compact Processing-in-Memory Graph Accelerator Alleviating
Sparsity and Redundancy},
booktitle = {Proceedings of the 41st {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2022, San Diego, California, USA, 30 October 2022
- 3 November 2022},
pages = {115:1--115:9},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3508352.3549372},
doi = {10.1145/3508352.3549372},
timestamp = {Tue, 14 Oct 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/LiALLZLSJL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/LuSLJL22,
author = {Heng Lu and
Zhuoran Song and
Xing Li and
Naifeng Jing and
Xiaoyao Liang},
title = {GCNTrain: {A} Unified and Efficient Accelerator for Graph Convolutional
Neural Network Training},
booktitle = {{IEEE} 40th International Conference on Computer Design, {ICCD} 2022,
Olympic Valley, CA, USA, October 23-26, 2022},
pages = {730--737},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ICCD56317.2022.00112},
doi = {10.1109/ICCD56317.2022.00112},
timestamp = {Tue, 14 Oct 2025 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccd/LuSLJL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/LiXSJCL22,
author = {Gang Li and
Weixiang Xu and
Zhuoran Song and
Naifeng Jing and
Jian Cheng and
Xiaoyao Liang},
title = {Ristretto: An Atomized Processing Architecture for Sparsity-Condensed
Stream Flow in {CNN}},
booktitle = {55th {IEEE/ACM} International Symposium on Microarchitecture, {MICRO}
2022, Chicago, IL, USA, October 1-5, 2022},
pages = {1434--1450},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/MICRO56248.2022.00097},
doi = {10.1109/MICRO56248.2022.00097},
timestamp = {Wed, 22 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/LiXSJCL22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2203-04570,
author = {Zhuoran Song and
Yihong Xu and
Zhezhi He and
Li Jiang and
Naifeng Jing and
Xiaoyao Liang},
title = {CP-ViT: Cascade Vision Transformer Pruning via Progressive Sparsity
Prediction},
journal = {CoRR},
volume = {abs/2203.04570},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2203.04570},
doi = {10.48550/ARXIV.2203.04570},
eprinttype = {arXiv},
eprint = {2203.04570},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2203-04570.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2203-05705,
author = {Zhuoran Song and
Yihong Xu and
Han Li and
Naifeng Jing and
Xiaoyao Liang and
Li Jiang},
title = {{DNN} Training Acceleration via Exploring {GPGPU} Friendly Sparsity},
journal = {CoRR},
volume = {abs/2203.05705},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2203.05705},
doi = {10.48550/ARXIV.2203.05705},
eprinttype = {arXiv},
eprint = {2203.05705},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2203-05705.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2210-15255,
author = {Yilong Zhao and
Li Jiang and
Mingyu Gao and
Naifeng Jing and
Chengyang Gu and
Qidong Tang and
Fangxin Liu and
Tao Yang and
Xiaoyao Liang},
title = {RePAST: {A} ReRAM-based {PIM} Accelerator for Second-order Training
of {DNN}},
journal = {CoRR},
volume = {abs/2210.15255},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2210.15255},
doi = {10.48550/ARXIV.2210.15255},
eprinttype = {arXiv},
eprint = {2210.15255},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2210-15255.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SongSCLJLJ21,
author = {Zhuoran Song and
Yanan Sun and
Lerong Chen and
Tianjian Li and
Naifeng Jing and
Xiaoyao Liang and
Li Jiang},
title = {{ITT-RNA:} Imperfection Tolerable Training for RRAM-Crossbar-Based
Deep Neural-Network Accelerator},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {40},
number = {1},
pages = {129--142},
year = {2021},
url = {https://doi.org/10.1109/TCAD.2020.2989373},
doi = {10.1109/TCAD.2020.2989373},
timestamp = {Wed, 01 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SongSCLJLJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiangLCCHSJMH21,
author = {Zhuojun Liang and
Dongxu Lv and
Chao Cui and
Hai{-}Bao Chen and
Weifeng He and
Weiguang Sheng and
Naifeng Jing and
Zhigang Mao and
Guanghui He},
title = {A 3.85-Gb/s 8 {\texttimes} 8 Soft-Output {MIMO} Detector With Lattice-Reduction-Aided
Channel Preprocessing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {29},
number = {2},
pages = {307--320},
year = {2021},
url = {https://doi.org/10.1109/TVLSI.2020.3036822},
doi = {10.1109/TVLSI.2020.3036822},
timestamp = {Thu, 04 Dec 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiangLCCHSJMH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asicon/SunGLTJ21,
author = {Yongshuai Sun and
Mengyu Guo and
Dacheng Liang and
Shan Tang and
Naifeng Jing},
editor = {Fan Ye and
Ting{-}Ao Tang},
title = {Exploiting Dynamic Bit Sparsity in Activation for Deep Neural Network
Acceleration},
booktitle = {14th {IEEE} International Conference on ASIC, {ASICON} 2021, Kunming,
China, October 26-29, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ASICON52560.2021.9620448},
doi = {10.1109/ASICON52560.2021.9620448},
timestamp = {Mon, 06 Dec 2021 11:20:15 +0100},
biburl = {https://dblp.org/rec/conf/asicon/SunGLTJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bigdatasec/ZhangJSWMJ21,
author = {Zihan Zhang and
Jianfei Jiang and
Weiguang Sheng and
Qin Wang and
Zhigang Mao and
Naifeng Jing},
title = {A Mapping Method for Reconfigurable Array based on Decoupled DataFlow},
booktitle = {7th {IEEE} International Conference on Big Data Security on Cloud,
{IEEE} International Conference on High Performance and Smart Computing,
and {IEEE} International Conference on Intelligent Data and Security,
BigDataSecurity/HPSC/IDS 2021, New York City, NY, USA, May 15-17,
2021},
pages = {180--185},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/BigDataSecurityHPSCIDS52275.2021.00042},
doi = {10.1109/BIGDATASECURITYHPSCIDS52275.2021.00042},
timestamp = {Wed, 22 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/bigdatasec/ZhangJSWMJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/YinWJSHMJ21,
author = {Chen Yin and
Qin Wang and
Jianfei Jiang and
Weiguang Sheng and
Guanghui He and
Zhigang Mao and
Naifeng Jing},
title = {Subgraph Decoupling and Rescheduling for Increased Utilization in
{CGRA} Architecture},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1394--1399},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474195},
doi = {10.23919/DATE51398.2021.9474195},
timestamp = {Fri, 05 Dec 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/YinWJSHMJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ZhaoHJLJ21,
author = {Yilong Zhao and
Zhezhi He and
Naifeng Jing and
Xiaoyao Liang and
Li Jiang},
editor = {Yiran Chen and
Victor V. Zhirnov and
Avesta Sasan and
Ioannis Savidis},
title = {Re2PIM: {A} Reconfigurable ReRAM-Based {PIM} Design for Variable-Sized
Vector-Matrix Multiplication},
booktitle = {{GLSVLSI} '21: Great Lakes Symposium on {VLSI} 2021, Virtual Event,
USA, June 22-25, 2021},
pages = {15--20},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3453688.3461494},
doi = {10.1145/3453688.3461494},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ZhaoHJLJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ShiSJHWJ21,
author = {Yongquan Shi and
Yongshuai Sun and
Jianfei Jiang and
Guanghui He and
Qin Wang and
Naifeng Jing},
title = {Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401762},
doi = {10.1109/ISCAS51556.2021.9401762},
timestamp = {Fri, 05 Dec 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ShiSJHWJ21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispa/WuSKJJL21,
author = {Feiyang Wu and
Zhuoran Song and
Jing Ke and
Li Jiang and
Naifeng Jing and
Xiaoyao Liang},
title = {PIPArch: Programmable Image Processing Architecture Using Sliding
Array},
booktitle = {2021 {IEEE} Intl Conf on Parallel {\&} Distributed Processing
with Applications, Big Data {\&} Cloud Computing, Sustainable
Computing {\&} Communications, Social Computing {\&} Networking
(ISPA/BDCloud/SocialCom/SustainCom), New York City, NY, USA, September
30 - Oct. 3, 2021},
pages = {73--80},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISPA-BDCloud-SocialCom-SustainCom52081.2021.00024},
doi = {10.1109/ISPA-BDCLOUD-SOCIALCOM-SUSTAINCOM52081.2021.00024},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispa/WuSKJJL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2103-01705,
author = {Fangxin Liu and
Wenbo Zhao and
Yilong Zhao and
Zongwu Wang and
Tao Yang and
Zhezhi He and
Naifeng Jing and
Xiaoyao Liang and
Li Jiang},
title = {{SME:} ReRAM-based Sparse-Multiplication-Engine to Squeeze-Out Bit
Sparsity of Neural Network},
journal = {CoRR},
volume = {abs/2103.01705},
year = {2021},
url = {https://arxiv.org/abs/2103.01705},
eprinttype = {arXiv},
eprint = {2103.01705},
timestamp = {Sat, 14 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2103-01705.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/remotesensing/ZhangSJJWM20,
author = {Yijia Zhang and
Weiguang Sheng and
Jianfei Jiang and
Naifeng Jing and
Qin Wang and
Zhigang Mao},
title = {Priority Branches for Ship Detection in Optical Remote Sensing Images},
journal = {Remote. Sens.},
volume = {12},
number = {7},
pages = {1196},
year = {2020},
url = {https://doi.org/10.3390/rs12071196},
doi = {10.3390/RS12071196},
timestamp = {Wed, 22 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/remotesensing/ZhangSJJWM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HeZJ20,
author = {Guanghui He and
Sijie Zheng and
Naifeng Jing},
title = {A Hierarchical Scrubbing Technique for {SEU} Mitigation on SRAM-Based
FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {10},
pages = {2134--2145},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.3010647},
doi = {10.1109/TVLSI.2020.3010647},
timestamp = {Thu, 04 Dec 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HeZJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/acsw/KeLLJLJ20,
author = {Jing Ke and
Changchang Liu and
Yizhou Lu and
Naifeng Jing and
Xiaoyao Liang and
Fusong Jiang},
editor = {Prem Prakash Jayaraman and
Dimitrios Georgakopoulos and
Timos K. Sellis and
Abdur Forkan},
title = {{FIMIL} : {A} high-throughput deep learning model for abnormality
detection with weak annotation in microscopy images},
booktitle = {Proceedings of the Australasian Computer Science Week, {ACSW} 2020,
Melbourne, VIC, Australia, February 3-7, 2020},
pages = {34:1--34:6},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3373017.3373051},
doi = {10.1145/3373017.3373051},
timestamp = {Fri, 15 Mar 2024 12:30:44 +0100},
biburl = {https://dblp.org/rec/conf/acsw/KeLLJLJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/aime/Ke0GWJL20,
author = {Jing Ke and
Yiqing Shen and
Yi Guo and
Jason D. Wright and
Naifeng Jing and
Xiaoyao Liang},
editor = {Martin Michalowski and
Robert Moskovitch},
title = {A High-Throughput Tumor Location System with Deep Learning for Colorectal
Cancer Histopathology Image},
booktitle = {Artificial Intelligence in Medicine - 18th International Conference
on Artificial Intelligence in Medicine, {AIME} 2020, Minneapolis,
MN, USA, August 25-28, 2020, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {12299},
pages = {260--269},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-59137-3\_24},
doi = {10.1007/978-3-030-59137-3\_24},
timestamp = {Wed, 16 Mar 2022 23:56:04 +0100},
biburl = {https://dblp.org/rec/conf/aime/Ke0GWJL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bibm/Ke0WJLS20,
author = {Jing Ke and
Yiqing Shen and
Jason D. Wright and
Naifeng Jing and
Xiaoyao Liang and
Dinggang Shen},
editor = {Taesung Park and
Young{-}Rae Cho and
Xiaohua Hu and
Illhoi Yoo and
Hyun Goo Woo and
Jianxin Wang and
Julio C. Facelli and
Seungyoon Nam and
Mingon Kang},
title = {Identifying patch-level {MSI} from histological images of Colorectal
Cancer by a Knowledge Distillation Model},
booktitle = {{IEEE} International Conference on Bioinformatics and Biomedicine,
{BIBM} 2020, Virtual Event, South Korea, December 16-19, 2020},
pages = {1043--1046},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/BIBM49941.2020.9313141},
doi = {10.1109/BIBM49941.2020.9313141},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/bibm/Ke0WJLS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SongWLJKLJ20,
author = {Zhuoran Song and
Jianfei Wang and
Tianjian Li and
Li Jiang and
Jing Ke and
Xiaoyao Liang and
Naifeng Jing},
title = {{GPNPU:} Enabling Efficient Hardware-Based Direct Convolution with
Multi-Precision Support in {GPU} Tensor Cores},
booktitle = {57th {ACM/IEEE} Design Automation Conference, {DAC} 2020, San Francisco,
CA, USA, July 20-24, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/DAC18072.2020.9218566},
doi = {10.1109/DAC18072.2020.9218566},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SongWLJKLJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YangLSLJJ20,
author = {Tao Yang and
Yunkun Liao and
Jianping Shi and
Yun Liang and
Naifeng Jing and
Li Jiang},
editor = {Nele Mentens and
Leonel Sousa and
Pedro Trancoso and
Miquel Peric{\`{a}}s and
Ioannis Sourdis},
title = {A Winograd-Based {CNN} Accelerator with a Fine-Grained Regular Sparsity
Pattern},
booktitle = {30th International Conference on Field-Programmable Logic and Applications,
{FPL} 2020, Gothenburg, Sweden, August 31 - September 4, 2020},
pages = {254--261},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/FPL50879.2020.00050},
doi = {10.1109/FPL50879.2020.00050},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/YangLSLJJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ZhangLG0HSMJ20,
author = {Zihan Zhang and
Taozhong Li and
Ning Guan and
Qin Wang and
Guanghui He and
Weiguang Sheng and
Zhigang Mao and
Naifeng Jing},
editor = {Tinoosh Mohsenin and
Weisheng Zhao and
Yiran Chen and
Onur Mutlu},
title = {Enabling Resistive-RAM-based Activation Functions for Deep Neural
Network Acceleration},
booktitle = {{GLSVLSI} '20: Great Lakes Symposium on {VLSI} 2020, Virtual Event,
China, September 7-9, 2020},
pages = {345--350},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3386263.3406915},
doi = {10.1145/3386263.3406915},
timestamp = {Sat, 18 Apr 2026 06:39:06 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ZhangLG0HSMJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpcc/JiangSLJ20,
author = {Zhaoming Jiang and
Zhuoran Song and
Xiaoyao Liang and
Naifeng Jing},
title = {PRArch: Pattern-Based Reconfigurable Architecture for Deep Neural
Network Acceleration},
booktitle = {22nd {IEEE} International Conference on High Performance Computing
and Communications; 18th {IEEE} International Conference on Smart
City; 6th {IEEE} International Conference on Data Science and Systems,
HPCC/SmartCity/DSS 2020, Yanuca Island, Cuvu, Fiji, December 14-16,
2020},
pages = {122--129},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/HPCC-SmartCity-DSS50907.2020.00016},
doi = {10.1109/HPCC-SMARTCITY-DSS50907.2020.00016},
timestamp = {Wed, 05 May 2021 11:23:31 +0200},
biburl = {https://dblp.org/rec/conf/hpcc/JiangSLJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/SongFWJ0JL20,
author = {Zhuoran Song and
Bangqi Fu and
Feiyang Wu and
Zhaoming Jiang and
Li Jiang and
Naifeng Jing and
Xiaoyao Liang},
title = {{DRQ:} Dynamic Region-based Quantization for Deep Neural Network Acceleration},
booktitle = {47th {ACM/IEEE} Annual International Symposium on Computer Architecture,
{ISCA} 2020, Virtual Event / Valencia, Spain, May 30 - June 3, 2020},
pages = {1010--1021},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCA45697.2020.00086},
doi = {10.1109/ISCA45697.2020.00086},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/SongFWJ0JL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HongGYWJJHJ20,
author = {Tu Hong and
Ning Guan and
Chen Yin and
Qin Wang and
Jianfei Jiang and
Jing Jin and
Guanghui He and
Naifeng Jing},
title = {Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable
Array},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9181275},
doi = {10.1109/ISCAS45731.2020.9181275},
timestamp = {Fri, 05 Dec 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/HongGYWJJHJ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WangGJLJZ20,
author = {Ran Wang and
Yuekang Guo and
Jing Jin and
Xiaoming Liu and
Naifeng Jing and
Jianjun Zhou},
title = {A Low Power Temperature-Compensated Common-Mode Voltage Detector for
Dynamic Amplifiers},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--4},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180689},
doi = {10.1109/ISCAS45731.2020.9180689},
timestamp = {Fri, 18 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/WangGJLJZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/SongWLKJL20,
author = {Zhuoran Song and
Feiyang Wu and
Xueyuan Liu and
Jing Ke and
Naifeng Jing and
Xiaoyao Liang},
title = {{VR-DANN:} Real-Time Video Recognition via Decoder-Assisted Neural
Network Acceleration},
booktitle = {53rd Annual {IEEE/ACM} International Symposium on Microarchitecture,
{MICRO} 2020, Athens, Greece, October 17-21, 2020},
pages = {698--710},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/MICRO50266.2020.00063},
doi = {10.1109/MICRO50266.2020.00063},
timestamp = {Wed, 11 Dec 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/SongWLKJL20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smartcloud/Zhou0JNLP20,
author = {Tao Zhou and
Yongxin Zhu and
Naifeng Jing and
Tianhao Nan and
Wanyi Li and
Bo Peng},
title = {Reliable SoC Design and Implementation of {SHA-3-HMAC} Algorithm with
Attack Protection},
booktitle = {{IEEE} International Conference on Smart Cloud, SmartCloud 2020, Washington,
DC, USA, November 6-8, 2020},
pages = {88--93},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/SmartCloud49737.2020.00025},
doi = {10.1109/SMARTCLOUD49737.2020.00025},
timestamp = {Thu, 03 Dec 2020 12:50:24 +0100},
biburl = {https://dblp.org/rec/conf/smartcloud/Zhou0JNLP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smartcom/Peng0JZZ20,
author = {B. O. Peng and
Yongxin Zhu and
Naifeng Jing and
Xiaoying Zheng and
Yueying Zhou},
editor = {Meikang Qiu},
title = {Design of a Hardware Accelerator for Zero-Knowledge Proof in Blockchains},
booktitle = {Smart Computing and Communication - 5th International Conference,
SmartCom 2020, Paris, France, December 29-31, 2020, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {12608},
pages = {136--145},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-74717-6\_15},
doi = {10.1007/978-3-030-74717-6\_15},
timestamp = {Tue, 20 Apr 2021 15:51:54 +0200},
biburl = {https://dblp.org/rec/conf/smartcom/Peng0JZZ20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/lgrs/ZhangHCJW19,
author = {Shuo Zhang and
Guanghui He and
Hai{-}Bao Chen and
Naifeng Jing and
Qin Wang},
title = {Scale Adaptive Proposal Network for Object Detection in Remote Sensing
Images},
journal = {{IEEE} Geosci. Remote. Sens. Lett.},
volume = {16},
number = {6},
pages = {864--868},
year = {2019},
url = {https://doi.org/10.1109/LGRS.2018.2888887},
doi = {10.1109/LGRS.2018.2888887},
timestamp = {Thu, 04 Dec 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/lgrs/ZhangHCJW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/SunGHWJMQJ19,
author = {Yanan Sun and
Jiawei Gu and
Weifeng He and
Qin Wang and
Naifeng Jing and
Zhigang Mao and
Weikang Qian and
Li Jiang},
title = {Energy-Efficient Nonvolatile {SRAM} Design Based on Resistive Switching
Multi-Level Cells},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {66-II},
number = {5},
pages = {753--757},
year = {2019},
url = {https://doi.org/10.1109/TCSII.2019.2908243},
doi = {10.1109/TCSII.2019.2908243},
timestamp = {Sun, 19 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/SunGHWJMQJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiWZJHJMJ19,
author = {Taozhong Li and
Qin Wang and
Yongxin Zhu and
Jianfei Jiang and
Guanghui He and
Jing Jin and
Zhigang Mao and
Naifeng Jing},
title = {A Novel Resistive Memory-based Process-in-memory Architecture for
Efficient Logic and Add Operations},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {24},
number = {2},
pages = {25:1--25:22},
year = {2019},
url = {https://doi.org/10.1145/3306495},
doi = {10.1145/3306495},
timestamp = {Fri, 05 Dec 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LiWZJHJMJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/JiangSSXXJZL19,
author = {Li Jiang and
Zhuoran Song and
Haiyue Song and
Chengwen Xu and
Qiang Xu and
Naifeng Jing and
Weifeng Zhang and
Xiaoyao Liang},
title = {Energy-Efficient and Quality-Assured Approximate Computing Framework
Using a Co-Training Method},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {24},
number = {6},
pages = {59:1--59:25},
year = {2019},
url = {https://doi.org/10.1145/3342239},
doi = {10.1145/3342239},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/JiangSSXXJZL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLJJS19,
author = {Qin Wang and
Zechen Liu and
Jianfei Jiang and
Naifeng Jing and
Weiguang Sheng},
title = {A New Cellular-Based Redundant {TSV} Structure for Clustered Faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {458--467},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2876906},
doi = {10.1109/TVLSI.2018.2876906},
timestamp = {Sun, 19 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLJJS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Ji0LJKL19,
author = {Houxiang Ji and
Li Jiang and
Tianjian Li and
Naifeng Jing and
Jing Ke and
Xiaoyao Liang},
editor = {Toshiyuki Shibuya},
title = {{HUBPA:} high utilization bidirectional pipeline architecture for
neuromorphic computing},
booktitle = {Proceedings of the 24th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2019, Tokyo, Japan, January 21-24, 2019},
pages = {249--254},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3287624.3287674},
doi = {10.1145/3287624.3287674},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/Ji0LJKL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/WangJKLJ19,
author = {Jianfei Wang and
Li Jiang and
Jing Ke and
Xiaoyao Liang and
Naifeng Jing},
editor = {Toshiyuki Shibuya},
title = {A sharing-aware {L1.5D} cache for data reuse in GPGPUs},
booktitle = {Proceedings of the 24th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2019, Tokyo, Japan, January 21-24, 2019},
pages = {388--393},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3287624.3287633},
doi = {10.1145/3287624.3287633},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/WangJKLJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhengYHWSJJJ19,
author = {Sijie Zheng and
Hongjun You and
Guanghui He and
Qin Wang and
Tao Si and
Jianfei Jiang and
Jing Jin and
Naifeng Jing},
title = {A Rapid Scrubbing Technique for {SEU} Mitigation on SRAM-Based FPGAs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702706},
doi = {10.1109/ISCAS.2019.8702706},
timestamp = {Fri, 05 Dec 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/ZhengYHWSJJJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangLJKGL18,
author = {Li Jiang and
Tianjian Li and
Naifeng Jing and
Nam Sung Kim and
Minyi Guo and
Xiaoyao Liang},
title = {CNFET-Based High Throughput {SIMD} Architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1331--1344},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2695899},
doi = {10.1109/TCAD.2017.2695899},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/JiangLJKGL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tpds/WangWJLLJ18,
author = {Jianfei Wang and
Qin Wang and
Li Jiang and
Chao Li and
Xiaoyao Liang and
Naifeng Jing},
title = {{IBOM:} An Integrated and Balanced On-Chip Memory for High Performance
GPGPUs},
journal = {{IEEE} Trans. Parallel Distributed Syst.},
volume = {29},
number = {3},
pages = {586--599},
year = {2018},
url = {https://doi.org/10.1109/TPDS.2017.2773516},
doi = {10.1109/TPDS.2017.2773516},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tpds/WangWJLLJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/fpga/SongSLDJLJ18,
author = {Haiyue Song and
Xiang Song and
Tianjian Li and
Hao Dong and
Naifeng Jing and
Xiaoyao Liang and
Li Jiang},
editor = {Jason Helge Anderson and
Kia Bazargan},
title = {A {FPGA} Friendly Approximate Computing Framework with Hybrid Neural
Networks: (Abstract Only)},
booktitle = {Proceedings of the 2018 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2018, Monterey, CA, USA, February 25-27, 2018},
pages = {286},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3174243.3174965},
doi = {10.1145/3174243.3174965},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SongSLDJLJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/iccad/PengCXJLL018,
author = {Zhenghao Peng and
Xuyang Chen and
Chengwen Xu and
Naifeng Jing and
Xiaoyao Liang and
Cewu Lu and
Li Jiang},
editor = {Iris Bahar},
title = {AXNet: approximate computing using an end-to-end trainable neural
network},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {11:1--11:8},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240783},
doi = {10.1145/3240765.3240783},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/PengCXJLL018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@inproceedings{DBLP:conf/iccad/SongX0SJL018,
author = {Haiyue Song and
Chengwen Xu and
Qiang Xu and
Zhuoran Song and
Naifeng Jing and
Xiaoyao Liang and
Li Jiang},
editor = {Iris Bahar},
title = {Invocation-driven neural approximate computing with a multiclass-classifier
and multiple approximators},
booktitle = {Proceedings of the International Conference on Computer-Aided Design,
{ICCAD} 2018, San Diego, CA, USA, November 05-08, 2018},
pages = {50},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3240765.3240819},
doi = {10.1145/3240765.3240819},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SongX0SJL018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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author = {Zhenghao Peng and
Xuyang Chen and
Chengwen Xu and
Naifeng Jing and
Xiaoyao Liang and
Cewu Lu and
Li Jiang},
title = {AXNet: ApproXimate computing using an end-to-end trainable neural
network},
journal = {CoRR},
volume = {abs/1807.10458},
year = {2018},
url = {http://arxiv.org/abs/1807.10458},
eprinttype = {arXiv},
eprint = {1807.10458},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1807-10458.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@article{DBLP:journals/corr/abs-1810-08379,
author = {Haiyue Song and
Chengwen Xu and
Qiang Xu and
Zhuoran Song and
Naifeng Jing and
Xiaoyao Liang and
Li Jiang},
title = {Invocation-driven Neural Approximate Computing with a Multiclass-Classifier
and Multiple Approximators},
journal = {CoRR},
volume = {abs/1810.08379},
year = {2018},
url = {http://arxiv.org/abs/1810.08379},
eprinttype = {arXiv},
eprint = {1810.08379},
timestamp = {Wed, 31 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-1810-08379.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
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@article{DBLP:journals/concurrency/WangFJLJ17,
author = {Jianfei Wang and
Fengfeng Fan and
Li Jiang and
Xiaoyao Liang and
Naifeng Jing},
title = {Incorporating selective victim cache into {GPGPU} for high-performance
computing},
journal = {Concurr. Comput. Pract. Exp.},
volume = {29},
number = {24},
year = {2017},
url = {https://doi.org/10.1002/cpe.4104},
doi = {10.1002/CPE.4104},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/concurrency/WangFJLJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JinHJHZSCJ17,
author = {Wei Jin and
Weifeng He and
Jianfei Jiang and
Haichao Huang and
Xuejun Zhao and
Yanan Sun and
Xin Chen and
Naifeng Jing},
title = {A 0.33 {V} 2.5 {\(\mu\)}W cross-point data-aware write structure,
read-half-select disturb-free sub-threshold {SRAM} in 130 nm {CMOS}},
journal = {Integr.},
volume = {58},
pages = {27--34},
year = {2017},
url = {https://doi.org/10.1016/j.vlsi.2017.02.001},
doi = {10.1016/J.VLSI.2017.02.001},
timestamp = {Sun, 23 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/JinHJHZSCJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JingJCZJLL17,
author = {Naifeng Jing and
Shunning Jiang and
Shuang Chen and
Jingjie Zhang and
Li Jiang and
Chao Li and
Xiaoyao Liang},
title = {Bank Stealing for a Compact and Efficient Register File Architecture
in {GPGPU}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {520--533},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2584623},
doi = {10.1109/TVLSI.2016.2584623},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JingJCZJLL17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LiBJLJ17,
author = {Tianjian Li and
Xiangyu Bi and
Naifeng Jing and
Xiaoyao Liang and
Li Jiang},
title = {Sneak-Path Based Test and Diagnosis for 1R {RRAM} Crossbar Using Voltage
Bias Technique},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {38:1--38:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062318},
doi = {10.1145/3061639.3062318},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LiBJLJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/XuWYXJLJ17,
author = {Chengwen Xu and
Xiangyu Wu and
Wenqi Yin and
Qiang Xu and
Naifeng Jing and
Xiaoyao Liang and
Li Jiang},
title = {On Quality Trade-off Control for Approximate Computing Using Iterative
Training},
booktitle = {Proceedings of the 54th Annual Design Automation Conference, {DAC}
2017, Austin, TX, USA, June 18-22, 2017},
pages = {52:1--52:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3061639.3062294},
doi = {10.1145/3061639.3062294},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/XuWYXJLJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/GaoXJJZ17,
author = {Xinchi Gao and
Licheng Xu and
Jing Jin and
Naifeng Jing and
Jianjun Zhou},
title = {A wideband simplified transformer-based {VCO} with digital amplitude
calibration},
booktitle = {{IEEE} 60th International Midwest Symposium on Circuits and Systems,
{MWSCAS} 2017, Boston, MA, USA, August 6-9, 2017},
pages = {787--790},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/MWSCAS.2017.8053041},
doi = {10.1109/MWSCAS.2017.8053041},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/mwscas/GaoXJJZ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/JingJZLFL16,
author = {Naifeng Jing and
Li Jiang and
Tao Zhang and
Chao Li and
Fengfeng Fan and
Xiaoyao Liang},
title = {Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs},
journal = {{IEEE} Trans. Computers},
volume = {65},
number = {1},
pages = {122--135},
year = {2016},
url = {https://doi.org/10.1109/TC.2015.2417545},
doi = {10.1109/TC.2015.2417545},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tc/JingJZLFL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiXLXCJJ16,
author = {Tianjian Li and
Feng Xie and
Xiaoyao Liang and
Qiang Xu and
Krishnendu Chakrabarty and
Naifeng Jing and
Li Jiang},
title = {A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {35},
number = {7},
pages = {1192--1205},
year = {2016},
url = {https://doi.org/10.1109/TCAD.2015.2512909},
doi = {10.1109/TCAD.2015.2512909},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiXLXCJJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/JingLZJSHM16,
author = {Naifeng Jing and
Taozhong Li and
Zhongyuan Zhao and
Wei Jin and
Yanan Sun and
Weifeng He and
Zhigang Mao},
editor = {Yuchen Song and
Shaojun Wang and
Brent Nelson and
Junbao Li and
Yu Peng},
title = {Enabling in-situ logic-in-memory capability using resistive-RAM crossbar
memory},
booktitle = {2016 International Conference on Field-Programmable Technology, {FPT}
2016, Xi'an, China, December 7-9, 2016},
pages = {233--236},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FPT.2016.7929541},
doi = {10.1109/FPT.2016.7929541},
timestamp = {Thu, 31 Jul 2025 21:24:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/JingLZJSHM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/LiJJKL16,
author = {Tianjian Li and
Li Jiang and
Naifeng Jing and
Nam Sung Kim and
Xiaoyao Liang},
title = {CNFET-based high throughput register file architecture},
booktitle = {34th {IEEE} International Conference on Computer Design, {ICCD} 2016,
Scottsdale, AZ, USA, October 2-5, 2016},
pages = {662--669},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ICCD.2016.7753354},
doi = {10.1109/ICCD.2016.7753354},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/LiJJKL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispdc/FanWJLJ16,
author = {Fengfeng Fan and
Jianfei Wang and
Li Jiang and
Xiaoyao Liang and
Naifeng Jing},
editor = {Riqing Chen and
Chunming Rong and
Dan Grigoras},
title = {Applying Victim Cache in High Performance {GPGPU} Computing},
booktitle = {15th International Symposium on Parallel and Distributed Computing,
{ISPDC} 2016, Fuzhou, China, July 8-10, 2016},
pages = {24--29},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISPDC.2016.12},
doi = {10.1109/ISPDC.2016.12},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispdc/FanWJLJ16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/JingWFYJLL16,
author = {Naifeng Jing and
Jianfei Wang and
Fengfeng Fan and
Wenkang Yu and
Li Jiang and
Chao Li and
Xiaoyao Liang},
title = {Cache-emulated register file: An integrated on-chip memory architecture
for high performance GPGPUs},
booktitle = {49th Annual {IEEE/ACM} International Symposium on Microarchitecture,
{MICRO} 2016, Taipei, Taiwan, October 15-19, 2016},
pages = {14:1--14:12},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/MICRO.2016.7783717},
doi = {10.1109/MICRO.2016.7783717},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/JingWFYJLL16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/ZhangJJSWL15,
author = {Tao Zhang and
Naifeng Jing and
Kaiming Jiang and
Wei Shu and
Min{-}You Wu and
Xiaoyao Liang},
title = {Buddy {SM:} Sharing Pipeline Front-End for Improved Energy Efficiency
in GPGPUs},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {12},
number = {2},
pages = {16:1--16:23},
year = {2015},
url = {https://doi.org/10.1145/2744202},
doi = {10.1145/2744202},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/ZhangJJSWL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/XieLXCJJ15,
author = {Feng Xie and
Xiaoyao Liang and
Qiang Xu and
Krishnendu Chakrabarty and
Naifeng Jing and
Li Jiang},
title = {Jump test for metallic CNTs in CNFET-based {SRAM}},
booktitle = {Proceedings of the 52nd Annual Design Automation Conference, San Francisco,
CA, USA, June 7-11, 2015},
pages = {16:1--16:6},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2744769.2744864},
doi = {10.1145/2744769.2744864},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/XieLXCJJ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/JingZJCHM15,
author = {Naifeng Jing and
Jiacheng Zhou and
Jianfei Jiang and
Xin Chen and
Weifeng He and
Zhigang Mao},
editor = {Diana Marculescu and
Frank Liu},
title = {Redundancy based Interconnect Duplication to Mitigate Soft Errors
in SRAM-based FPGAs},
booktitle = {Proceedings of the {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2015, Austin, TX, USA, November 2-6, 2015},
pages = {764--769},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICCAD.2015.7372647},
doi = {10.1109/ICCAD.2015.7372647},
timestamp = {Mon, 26 Jun 2023 16:43:56 +0200},
biburl = {https://dblp.org/rec/conf/iccad/JingZJCHM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/JingCJJLL15,
author = {Naifeng Jing and
Shuang Chen and
Shunning Jiang and
Li Jiang and
Chao Li and
Xiaoyao Liang},
title = {Bank stealing for conflict mitigation in {GPGPU} Register File},
booktitle = {{IEEE/ACM} International Symposium on Low Power Electronics and Design,
{ISLPED} 2015, Rome, Italy, July 22-24, 2015},
pages = {55--60},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISLPED.2015.7273490},
doi = {10.1109/ISLPED.2015.7273490},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/JingCJJLL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/WuXJL15,
author = {Xiangyu Wu and
Yuanfang Xia and
Naifeng Jing and
Xiaoyao Liang},
title = {CGSharing: Efficient content sharing in GPU-based cloud gaming},
booktitle = {{IEEE/ACM} International Symposium on Low Power Electronics and Design,
{ISLPED} 2015, Rome, Italy, July 22-24, 2015},
pages = {171--176},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISLPED.2015.7273509},
doi = {10.1109/ISLPED.2015.7273509},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/WuXJL15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/JiangPJLLX15,
author = {Li Jiang and
Pu Pang and
Naifeng Jing and
Sung Kyu Lim and
Xiaoyao Liang and
Qiang Xu},
title = {On diagnosable and tunable 3D clock network design for lifetime reliability
enhancement},
booktitle = {2015 {IEEE} International Test Conference, {ITC} 2015, Anaheim, CA,
USA, October 6-8, 2015},
pages = {1--10},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/TEST.2015.7342405},
doi = {10.1109/TEST.2015.7342405},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/JiangPJLLX15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/ZhaoSJHM15,
author = {Zhongyuan Zhao and
Weiguang Sheng and
Naifeng Jing and
Weifeng He and
Zhigang Mao},
editor = {Michael H{\"{u}}bner and
Maya B. Gokhale and
Ren{\'{e}} Cumplido},
title = {Resource-saving compile flow for coarse-grained reconfigurable architectures},
booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
2015, Riviera Maya, Mexico, December 7-9, 2015},
pages = {1--8},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ReConFig.2015.7393353},
doi = {10.1109/RECONFIG.2015.7393353},
timestamp = {Wed, 20 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/ZhaoSJHM15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/WangJHLLJQ15,
author = {Chen Wang and
Li Jiang and
Shiyan Hu and
Tianjian Li and
Xiaoyao Liang and
Naifeng Jing and
Weikang Qian},
title = {Timing-driven placement for carbon nanotube circuits},
booktitle = {28th {IEEE} International System-on-Chip Conference, {SOCC} 2015,
Beijing, China, September 8-11, 2015},
pages = {362--367},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/SOCC.2015.7406983},
doi = {10.1109/SOCC.2015.7406983},
timestamp = {Tue, 24 Mar 2026 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/socc/WangJHLLJQ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/0002JH14,
author = {Zhe Feng and
Naifeng Jing and
Lei He},
title = {{IPF:} In-Place X-Filling Algorithm for the Reliability of Modern
FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {10},
pages = {2225--2228},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2282819},
doi = {10.1109/TVLSI.2013.2282819},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/0002JH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/JingSLGMGCL13,
author = {Naifeng Jing and
Yao Shen and
Yao Lu and
Shrikanth Ganapathy and
Zhigang Mao and
Minyi Guo and
Ramon Canal and
Xiaoyao Liang},
editor = {Avi Mendelson},
title = {An energy-efficient and scalable eDRAM-based register file architecture
for {GPGPU}},
booktitle = {The 40th Annual International Symposium on Computer Architecture,
ISCA'13, Tel-Aviv, Israel, June 23-27, 2013},
pages = {344--355},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2485922.2485952},
doi = {10.1145/2485922.2485952},
timestamp = {Fri, 09 Jul 2021 15:51:20 +0200},
biburl = {https://dblp.org/rec/conf/isca/JingSLGMGCL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/JingLLL13,
author = {Naifeng Jing and
Haopeng Liu and
Yao Lu and
Xiaoyao Liang},
editor = {Pai H. Chou and
Ru Huang and
Yuan Xie and
Tanay Karnik},
title = {Compiler assisted dynamic register file in {GPGPU}},
booktitle = {International Symposium on Low Power Electronics and Design (ISLPED),
Beijing, China, September 4-6, 2013},
pages = {3--8},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISLPED.2013.6629258},
doi = {10.1109/ISLPED.2013.6629258},
timestamp = {Thu, 06 Jun 2024 10:53:08 +0200},
biburl = {https://dblp.org/rec/conf/islped/JingLLL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/JingL0HMH12,
author = {Naifeng Jing and
Ju{-}Yueh Lee and
Zhe Feng and
Weifeng He and
Zhigang Mao and
Lei He},
title = {{SEU} fault evaluation and characteristics for SRAM-based {FPGA} architectures
and synthesis algorithms},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {18},
number = {1},
pages = {13:1--13:18},
year = {2012},
url = {https://doi.org/10.1145/2390191.2390204},
doi = {10.1145/2390191.2390204},
timestamp = {Sun, 19 Jan 2025 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/JingL0HMH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/LeeCJSWWH12,
author = {Ju{-}Yueh Lee and
Cheng{-}Ru Chang and
Naifeng Jing and
Juexiao Su and
Shi{-}Jie Wen and
Rick Wong and
Lei He},
title = {Heterogeneous configuration memory scrubbing for soft error mitigation
in FPGAs},
booktitle = {2012 International Conference on Field-Programmable Technology, {FPT}
2012, Seoul, Korea (South), December 10-12, 2012},
pages = {23--28},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPT.2012.6412105},
doi = {10.1109/FPT.2012.6412105},
timestamp = {Fri, 22 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/LeeCJSWWH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/GeJHM12,
author = {Bingjing Ge and
Naifeng Jing and
Weifeng He and
Zhigang Mao},
title = {Contention and energy aware mapping for real-time applications on
Network-on-Chip},
booktitle = {International SoC Design Conference, {ISOCC} 2012, Jeju Island, South
Korea, November 4-7, 2012},
pages = {72--76},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISOCC.2012.6407042},
doi = {10.1109/ISOCC.2012.6407042},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isocc/GeJHM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JingLZTMH11,
author = {Naifeng Jing and
Ju{-}Yueh Lee and
Chun Zhang and
Jiarong Tong and
Zhigang Mao and
Lei He},
editor = {John Wawrzynek and
Katherine Compton},
title = {Fault modeling and characteristics of SRAM-based FPGAs (abstract only)},
booktitle = {Proceedings of the {ACM/SIGDA} 19th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2011, Monterey, California, USA,
February 27, March 1, 2011},
pages = {279},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1950413.1950471},
doi = {10.1145/1950413.1950471},
timestamp = {Mon, 01 Jun 2026 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/JingLZTMH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/JingLFHMWWH11,
author = {Naifeng Jing and
Ju{-}Yueh Lee and
Zhe Feng and
Weifeng He and
Zhigang Mao and
Shi{-}Jie Wen and
Rick Wong and
Lei He},
title = {Quantitative {SEU} Fault Evaluation for SRAM-Based {FPGA} Architectures
and Synthesis Algorithms},
booktitle = {International Conference on Field Programmable Logic and Applications,
{FPL} 2011, September 5-7, Chania, Crete, Greece},
pages = {282--285},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/FPL.2011.57},
doi = {10.1109/FPL.2011.57},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/JingLFHMWWH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/FengJCHH11,
author = {Zhe Feng and
Naifeng Jing and
GengSheng Chen and
Yu Hu and
Lei He},
title = {{IPF:} In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs},
booktitle = {International Conference on Field Programmable Logic and Applications,
{FPL} 2011, September 5-7, Chania, Crete, Greece},
pages = {482--485},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/FPL.2011.95},
doi = {10.1109/FPL.2011.95},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/FengJCHH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/JingLHMH11,
author = {Naifeng Jing and
Ju{-}Yueh Lee and
Weifeng He and
Zhigang Mao and
Lei He},
editor = {Joel R. Phillips and
Alan J. Hu and
Helmut Graeb},
title = {Mitigating {FPGA} interconnect soft errors by in-place {LUT} inversion},
booktitle = {2011 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2011, San Jose, California, USA, November 7-10, 2011},
pages = {582--586},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICCAD.2011.6105389},
doi = {10.1109/ICCAD.2011.6105389},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/JingLHMH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/XieHJM11,
author = {Li Xie and
Weifeng He and
Naifeng Jing and
Zhigang Mao},
title = {A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable
processor},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2011), May
15-19 2011, Rio de Janeiro, Brazil},
pages = {1952--1955},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISCAS.2011.5937972},
doi = {10.1109/ISCAS.2011.5937972},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/XieHJM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JingHM11,
author = {Naifeng Jing and
Weifeng He and
Zhigang Mao},
title = {A general statistical estimation for application mapping in Network-on-Chip},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {172--175},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081669},
doi = {10.1109/VLSISOC.2011.6081669},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/JingHM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JingHZM10,
author = {Naifeng Jing and
Weifeng He and
Yongxin Zhu and
Zhigang Mao},
title = {Statistical estimation and evaluation for communication mapping in
Network-on-Chip},
journal = {Integr.},
volume = {43},
number = {2},
pages = {220--229},
year = {2010},
url = {https://doi.org/10.1016/j.vlsi.2009.10.002},
doi = {10.1016/J.VLSI.2009.10.002},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JingHZM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/JingHM10,
author = {Naifeng Jing and
Weifeng He and
Zhigang Mao},
editor = {Thomas B{\"{u}}chner and
Ramalingam Sridhar and
Andrew Marshall and
Norbert Schuhmann},
title = {Resource constrained mapping of data flow graphs onto coarse-grained
reconfigurable array},
booktitle = {Annual {IEEE} International SoC Conference, SoCC 2010, September 27-29,
2010, Las Vegas, NV, USA, Proceedings},
pages = {260--265},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/SOCC.2010.5784756},
doi = {10.1109/SOCC.2010.5784756},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/JingHM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icess/JingMZ09,
author = {Naifeng Jing and
Zhigang Mao and
Yongxin Zhu},
editor = {Tianzhou Chen and
Dimitrios N. Serpanos and
Walid Taha},
title = {Statistical Estimation for Total Communication Load in Application-Specific
Network-on-Chip},
booktitle = {International Conference on Embedded Software and Systems, {ICESS}
'09, Hangzhou, Zhejiang, P. R. China, May 25-27, 2009},
pages = {109--114},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ICESS.2009.75},
doi = {10.1109/ICESS.2009.75},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icess/JingMZ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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