A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. - Ryu, Yesin; Kwon, Young-Cheon; Lee, Jaehoon; Ahn, Sung-Gi; Park, Jaewon; Lee, Kijun; Choi, Yu Ho; Cho, Han-Won; Kim, Jae San; Lee, Jungyu; Lee, Haesuk; Song, Seung Ho; et al. (2022)

Design and Analysis of Low Power and High SFDR Direct Digital Frequency Synthesizer. - Choi, Ji-Min; Yoon, Dong-Hyun; Jung, Dong-Kyu; Seong, Kiho; Han, Jae-Soub; Lee, Woojoo; Baek, Kwang-Hyun (IEEE Access, 2020)

LW-DEM: Designing a Low Power Digital-to-Analog Converter Using Lightweight Dynamic Element Matching Technique. - Yoon, Dong-Hyun; Jung, Dong-Kyu; Jung, Bo-Yun; Choi, Ji-Min; Jo, Yongjun; Lee, Sukho; Lee, Woojoo; Baek, Kwang-Hyun (IEEE Access, 2019)