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Aileen B. Caberos
2020 – today
- 2023
- [c7]Edwin C. Cuizon, Marven A. Yuson, Aileen B. Caberos, Nieva M. Mapula, Harreez M. Villaruz:
Design of Charge Pump for Low Power, Wide Range PLL in 65nm CMOS Technology. ISCIT 2023: 1-5
2010 – 2019
- 2019
- [c6]Ecclesiastes G. Montaos, Aileen B. Caberos, Leocarl M. Viñalon:
An Area-Efficient and Low-Power Comparator for Type-III Compensated Voltage-Mode Control DC-DC Buck Converter in 65nm CMOS Technology Process. ISCIT 2019: 113-117 - [c5]Leocarl M. Viñalon, Aileen B. Caberos, Olga Joy Labajo-Gerasta:
A Modified Yadav CMOS Buffer for SRAM Design. ISCIT 2019: 122-126 - [c4]Roy Venzon C. Adrivan, Raymond Kyle G. Conde, Aileen B. Caberos, Chandler Timm C. Doloriel:
An Energy Combiner for Multi-Source Energy Harvesting with Charge Control. ISCIT 2019: 371-376 - [c3]Daryl P. Pongcol, Olga Joy Labajo-Gerasta, Jesrey Martin S. Macasero, Vrian Jay V. Ylaya, Najie M. Pandian, Aileen B. Caberos:
Frequency Shift Keying Radar for Ground Object Detection in GNU-Radio with USRP. ISCIT 2019: 442-447 - [c2]Vrian Jay V. Ylaya, Anna Ruth Alvarez, Potrinordid'dan Benasing, Olga Joy Labajo-Gerasta, Aileen B. Caberos, Najie M. Pandian:
Artificial Intelligent (AI) Signal Processing Approach of Subsurface Electromagnetic Radar. ISCIT 2019: 452-457 - [c1]Chandler Timm C. Doloriel, Aileen B. Caberos:
High Speed CMOS Pulse Generator Based on Analog Ramp Signal Implemented in 65nm CMOS Process Technology. ISCIT 2019: 578-583
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last updated on 2024-10-07 21:23 CEST by the dblp team
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