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Hortensia Mecha
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2020 – today
- 2023
- [j12]Juan Carlos Fabero
, Golnaz Korkian
SEE sensitivity of a COTS 28-nm SRAM-based FPGA under thermal neutrons and different incident angles. Microprocess. Microsystems 96: 104743 (2023) - 2022
- [j11]Golnaz Korkian
Single Event Upsets Under Proton, Thermal, and Fast Neutron Irradiation in Emerging Nonvolatile Memories. IEEE Access 10: 114566-114585 (2022) - 2021
- [c17]Juan Carlos Fabero, Golnaz Korkian, Francisco J. Franco, Hortensia Mecha, Manon Letiche, Juan Antonio Clemente:
Thermal Neutron-induced SEUs on a COTS 28-nm SRAM-based FPGA under Different Incident Angles. LATS 2021: 1-6 - [c16]Mohammadreza Rezaei, Francisco J. Franco, Juan Carlos Fabero, Hortensia Mecha, Helmut Puchner, Juan Antonio Clemente:
Impact of DVS on Power Consumption and SEE Sensitivity of COTS Volatile SRAMs. LATS 2021: 1-6 - 2020
- [j10]Adrián Alcolea Morena
Analysis of a Pipelined Architecture for Sparse DNNs on Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 1993-2003 (2020)
2010 – 2019
- 2018
- [j9]Javier Olivito, Felipe Serrano
Analysis of the reconfiguration latency and energy overheads for a Xilinx Virtex-5 field-programmable gate array. IET Comput. Digit. Tech. 12(4): 150-157 (2018) - 2016
- [j8]Juan Antonio Clemente
Hardware implementation of a fault-tolerant Hopfield Neural Network on FPGAs. Neurocomputing 171: 1606-1609 (2016) - [c15]Marcos Sánchez-Élez, Inmaculada Pardines, Felipe Serrano, Hortensia Mecha:
Radiation-hardened DSP configurations for implementing arithmetic functions on FPGA. DATE 2016: 1501-1504 - 2010
- [c14]Sara Román Navarro, Hortensia Mecha, Daniel Mozos:
A Constant Complexity Allocation Algorithm for Reconfigurable Systems Management Adapted to Heterogeneous Workload Profiles. ERSA 2010: 259-262
2000 – 2009
- 2009
- [c13]Jose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha
3D FPGA resource management and fragmentation metric for hardware multitasking. IPDPS 2009: 1-7 - 2008
- [j7]S. Roman, Hortensia Mecha
Constant complexity scheduling for hardware multitasking in two dimensional reconfigurable field-programmable gate arrays. IET Comput. Digit. Tech. 2(6): 401-412 (2008) - [j6]Jesús Tabero
Allocation heuristics and defragmentation measures for reconfigurable systems management. Integr. 41(2): 281-296 (2008) - [c12]Angel Luis González Bravo, Hortensia Mecha, Julio Septién, Sara Román Navarro, Daniel Mozos:
Synthesis of relocatable tasks and implementation of a task communication bus in a general purpose Hw system. ERSA 2008: 307-308 - [c11]Laura Sánchez, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo:
FPGA Resource Management Using Internal RAM as Aata Cache. ERSA 2008: 317-318 - [c10]Jose Antonio Valero, Julio Septién, Daniel Mozos, Hortensia Mecha, Angel Luis González Bravo:
Resource Management for Hw Multitasking in Three Dimensional FPGAs. ERSA 2008: 319-320 - [c9]Julio Septién, Daniel Mozos, Hortensia Mecha
Perimeter quadrature-based metric for estimating FPGA fragmentation in 2D HW multitasking. IPDPS 2008: 1-8 - 2006
- [c8]Sara Román Navarro, Julio Septién, Hortensia Mecha, Daniel Mozos:
Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs. ARC 2006: 187-192 - [c7]Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos:
Task placement heuristic based on 3D-adjacency and look-ahead in reconfigurable systems. ASP-DAC 2006: 396-401 - [c6]Sara Román Navarro, Hortensia Mecha
Partition Based Dynamic 2D HW Multitasking Management. DSD 2006: 61-70 - [c5]Julio Septién, Hortensia Mecha
2D defragmentation heuristics for hardware multitasking on reconfigurable devices. IPDPS 2006 - 2004
- [c4]Jesús Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos:
A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management. FPL 2004: 241-250 - 2003
- [j5]Javier Resano
Analyzing communication overheads during hardware/software partitioning. Microelectron. J. 34(11): 1001-1007 (2003) - [c3]Javier Resano, Daniel Mozos, Elena Pérez-Miñana, Hortensia Mecha, Julio Septién:
A Hardware/Software Partitioning and Scheduling Approach for Embedded Systems with Low-Power and High Performance Requirements. PATMOS 2003: 580-589
1990 – 1999
- 1999
- [j4]Katzalin Olcoz
Unified data path allocation and BIST intrusion. Integr. 28(1): 55-99 (1999) - 1998
- [c2]Juan Antonio Maestro
A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process. DATE 1998: 218-225 - 1997
- [j3]R. Moreno, Román Hermida
A unified approach for scheduling and allocation. Integr. 23(1): 1-35 (1997) - [c1]Hortensia Mecha, Milagros Fernández:
Interconnection Delay and Clock Cycle Selection in High Level Synthesis. VLSI Design 1997: 504-505 - 1996
- [j2]Hortensia Mecha
A method for area estimation of data-path in high level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 258-265 (1996) - 1994
- [j1]Hortensia Mecha
Clock cycle estimation based on dead time and control unit area minimization. Microprocess. Microprogramming 40(10-12): 821-824 (1994)
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