default search action
Nader Bagherzadeh
Person information
- affiliation: University of California Irvine, CA, USA
- affiliation (PhD 1987): University of Texas at Austin, TX, USA
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
- [i8]Ali Sedaghatgoo, Amir M. Hajisadeghi, Mahmoud Momtazpour, Nader Bagherzadeh:
ARMAN: A Reconfigurable Monolithic 3D Accelerator Architecture for Convolutional Neural Networks. CoRR abs/2402.04431 (2024) - 2023
- [j141]Ehsan Faghih, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh:
Efficient realization of quantum balanced ternary reversible multiplier building blocks: A great step towards sustainable computing. Sustain. Comput. Informatics Syst. 40: 100908 (2023) - [j140]Andrew Ding
, Ye Qiao
BNN An Ideal Architecture for Acceleration With Resistive in Memory Computation. IEEE Trans. Emerg. Top. Comput. 11(2): 281-291 (2023) - [i7]Shima Nabiee, Nader Bagherzadeh:
Stock Trend Prediction: A Semantic Segmentation Approach. CoRR abs/2303.09323 (2023) - [i6]Harsimrat Kaeley, Ye Qiao, Nader Bagherzadeh:
Support for Stock Trend Prediction Using Transformers and Sentiment Analysis. CoRR abs/2305.14368 (2023) - 2022
- [j139]Diganta Sengupta
Reversible quantum communication & systems. IET Quantum Commun. 3(1): 1-4 (2022) - [j138]Hyunjin Kim
A storage-efficient ensemble classification using filter sharing on binarized convolutional neural networks. PeerJ Comput. Sci. 8: e924 (2022) - [j137]Daniele Jahier Pagliari
Guest Editorial: Thematic Section on Applications of Emerging Computing Technologies in Smart Manufacturing and Industry 4.0. IEEE Trans. Emerg. Top. Comput. 10(1): 6-8 (2022) - [j136]Min Soo Kim
The Effects of Approximate Multiplication on Convolutional Neural Networks. IEEE Trans. Emerg. Top. Comput. 10(2): 904-916 (2022) - [j135]Maryam S. Hosseini
Near Volatile and Non-Volatile Memory Processing in 3D Systems. IEEE Trans. Emerg. Top. Comput. 10(3): 1657-1664 (2022) - [j134]Raul Murillo
PLAM: A Posit Logarithm-Approximate Multiplier. IEEE Trans. Emerg. Top. Comput. 10(4): 2079-2085 (2022) - [c134]Ye Qiao
A Two-Stage Efficient 3-D CNN Framework for EEG Based Emotion Recognition. ICIT 2022: 1-8 - [i5]Ye Qiao, Mohammed Alnemari, Nader Bagherzadeh:
A Two-Stage Efficient 3-D CNN Framework for EEG Based Emotion Recognition. CoRR abs/2208.00883 (2022) - 2021
- [j133]Mina Chookhachizadeh Moghadam, Ehsan Masoumi Khalil Abad, Samir Kendale
Predicting hypotension in the ICU using noninvasive physiological signals. Comput. Biol. Medicine 129: 104120 (2021) - [j132]Seyedeh Yasaman Hosseini Mirmahaleh
Data scheduling and placement in deep learning accelerator. Clust. Comput. 24(4): 3651-3669 (2021) - [j131]Javad Talafy
A High Performance, Multi-Bit Output Logic-in-Memory Adder. IEEE Trans. Emerg. Top. Comput. 9(4): 2223-2233 (2021) - [j130]Masoomeh Jasemi
Enhancing Reliability of Emerging Memory Technology for Machine Learning Accelerators. IEEE Trans. Emerg. Top. Comput. 9(4): 2234-2240 (2021) - [c133]Maryam S. Hosseini, Masoumeh Ebrahimi, Pooria M. Yaghini, Nader Bagherzadeh:
Application Characterization for Near Memory Processing. PDP 2021: 148-152 - [i4]Raul Murillo
PLAM: a Posit Logarithm-Approximate Multiplier for Power Efficient Posit-based DNNs. CoRR abs/2102.09262 (2021) - 2020
- [j129]Hongzhi Zhao
A Fine-Grained Source-Throttling Method for Mesh Architectures. IEEE Access 8: 33101-33112 (2020) - [j128]Mina Chookhachizadeh Moghadam, Ehsan Masoumi Khalil Abad, Nader Bagherzadeh
A machine-learning approach to predicting hypotensive events in ICU settings. Comput. Biol. Medicine 118: 103626 (2020) - [j127]Masoomeh Jasemi, Shaahin Hessabi
Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators. Comput. Electr. Eng. 86: 106698 (2020) - [j126]Ali Bozorgmehr, Mohammad Khaleqi Qaleh Jooq, Mohammad Hossein Moaiyeri
A novel digital fuzzy system for image edge detection based on wrap-gate carbon nanotube transistors. Comput. Electr. Eng. 87: 106811 (2020) - [j125]Sahar Nikbakht Aali
Divisible load scheduling of image processing applications on the heterogeneous star and tree networks using a new genetic algorithm. Concurr. Comput. Pract. Exp. 32(10) (2020) - [j124]Seyedeh Yasaman Hosseini Mirmahaleh
Flow mapping on mesh-based deep learning accelerator. J. Parallel Distributed Comput. 144: 80-97 (2020) - [j123]Alireza Tajary, Hamid R. Zarandi, Nader Bagherzadeh:
IRHT: An SDC detection and recovery architecture based on value locality of instruction binary codes. Microprocess. Microsystems 77: 103159 (2020) - [j122]Ahmad Albaqsami
Adaptive HTF-MPR: An Adaptive Heterogeneous TensorFlow Mapper Utilizing Bayesian Optimization and Genetic Algorithms. ACM Trans. Intell. Syst. Technol. 11(5): 55:1-55:25 (2020) - [c132]Mina Chookhachizadeh Moghadam, Ehsan Masoumi Khalil Abad, Nader Bagherzadeh, Davinder Ramsingh, Zeev N. Kain:
Supervised Machine-Learning Algorithms in Real-time Prediction of Hypotensive Events. EMBC 2020: 5468-5471 - [c131]Lulwah Alhubail, Masoomeh Jasemi, Nader Bagherzadeh:
NoC Design Methodologies for Heterogeneous Architecture. PDP 2020: 299-306 - [c130]Sina Shahhosseini, Ahmad Albaqsami, Masoomeh Jasemi, Nader Bagherzadeh:
Partition Pruning: Parallelization-Aware Pruning for Dense Neural Networks. PDP 2020: 307-311 - [i3]Masoomeh Jasemi, Shaahin Hessabi, Nader Bagherzadeh:
Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators. CoRR abs/2001.08806 (2020) - [i2]Min Soo Kim, Alberto A. Del Barrio, Hyunjin Kim, Nader Bagherzadeh:
Effects of Approximate Multiplication on Convolutional Neural Networks. CoRR abs/2007.10500 (2020)
2010 – 2019
- 2019
- [j121]Sepehr Tabrizchi
Novel CNFET ternary circuit techniques for high-performance and energy-efficient design. IET Circuits Devices Syst. 13(2): 193-202 (2019) - [j120]Amin Mehranzadeh
DICA: destination intensity and congestion-aware output selection strategy for network-on-chip systems. IET Comput. Digit. Tech. 13(4): 335-347 (2019) - [j119]Mahdi Torabzadehkashi
Computational storage: an efficient and scalable platform for big data and HPC applications. J. Big Data 6: 100 (2019) - [j118]Luis German Garcia Morales, Jose Edinson Aedo Cobo, Nader Bagherzadeh
A new approach to the Population-Based Incremental Learning algorithm using virtual regions for task mapping on NoCs. J. Syst. Archit. 97: 443-454 (2019) - [j117]Mona Soleymani
CLBM: Controlled load-balancing mechanism for congestion management in silicon interposer NoC architecture. J. Syst. Archit. 98: 102-113 (2019) - [j116]Maryam Toulabinejad, MohammadReza Taheri, Keivan Navi, Nader Bagherzadeh
Toward efficient implementation of basic balanced ternary arithmetic operations in CNFET technology. Microelectron. J. 90: 267-277 (2019) - [j115]Min Soo Kim
Efficient Mitchell's Approximate Log Multipliers for Convolutional Neural Networks. IEEE Trans. Computers 68(5): 660-675 (2019) - [c129]Hyun Jin Kim, Min Soo Kim, Alberto A. Del Barrio
A Cost-Efficient Iterative Truncated Logarithmic Multiplication for Convolutional Neural Networks. ARITH 2019: 108-111 - [c128]Lulwah Alhubail, Nader Bagherzadeh
Power and Performance Optimal NoC Design for CPU-GPU Architecture Using Formal Models. DATE 2019: 634-637 - [c127]Mohammed Alnemari
Efficient Deep Neural Networks for Edge Computing. EDGE 2019: 1-7 - [c126]Leonardo Tavares Oliveira, Min Soo Kim, Alberto A. Del Barrio García, Nader Bagherzadeh, Ricardo Menotti:
Design of Power-Efficient FPGA Convolutional Cores with Approximate Log Multiplier. ESANN 2019 - [c125]Mahdi Torabzadehkashi
Accelerating HPC Applications Using Computational Storage Devices. HPCC/SmartCity/DSS 2019: 1878-1885 - [c124]Saba Mohammadi, Masoomeh Jasemi, Seyed Mohammadjavad Seyed Talebi, Nader Bagherzadeh
A Radiation Hard Sense Circuit for Spin Transfer Torque Random Access Memory. ISCAS 2019: 1-5 - [c123]Seyedeh Yasaman Hosseini Mirmahaleh
Flow mapping and data distribution on mesh-based deep learning accelerator. NOCS 2019: 13:1-13:8 - [c122]Mahdi Torabzadehkashi
Catalina: In-Storage Processing Acceleration for Scalable Big Data Analytics. PDP 2019: 430-437 - [i1]Sina Shahhosseini, Ahmad Albaqsami, Masoomeh Jasemi, Shaahin Hessabi, Nader Bagherzadeh:
Partition Pruning: Parallelization-Aware Pruning for Deep Neural Networks. CoRR abs/1901.11391 (2019) - 2018
- [j114]Fatemeh Khodaparast, Midia Reshadi, Nader Bagherzadeh
Application partitioning and mapping for bypass channel based NoC. Comput. Electr. Eng. 71: 676-691 (2018) - [j113]Amir Fadakar Noghondar, Midia Reshadi, Nader Bagherzadeh
Reducing bypass-based network-on-chip latency using priority mechanism. IET Comput. Digit. Tech. 12(1): 1-8 (2018) - [j112]Atefehsadat Haghighathoseini, Hossein Bobarshad
Hospital enterprise Architecture Framework (Study of Iranian University Hospital Organization). Int. J. Medical Informatics 114: 88-100 (2018) - [j111]Armineh Arasteh, Mohammad Hossein Moaiyeri
An energy and area efficient 4: 2 compressor based on FinFETs. Integr. 60: 224-231 (2018) - [j110]Ayed Alqahtani, Zongqing Ren, Jaeho Lee, Nader Bagherzadeh
System-Level Analysis of 3D ICs with Thermal TSVs. ACM J. Emerg. Technol. Comput. Syst. 14(3): 37:1-37:16 (2018) - [j109]Fahimeh Danehdaran, Milad Bagherian Khosroshahy
Design and Power Analysis of New Coplanar One-Bit Full-Adder Cell in Quantum-Dot Cellular Automata. J. Low Power Electron. 14(1): 38-48 (2018) - [j108]Michael Opoku Agyeman
Energy and performance-aware application mapping for inhomogeneous 3D networks-on-chip. J. Syst. Archit. 89: 103-117 (2018) - [j107]Zana Ghaderi
STABLE: Stress-Aware Boolean Matching to Mitigate BTI-Induced SNM Reduction in SRAM-Based FPGAs. IEEE Trans. Computers 67(1): 102-114 (2018) - [j106]Freek Verbeek
A Compositional Approach for Verifying Protocols Running on On-Chip Networks. IEEE Trans. Computers 67(7): 905-919 (2018) - [j105]Ronak Salamat
LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification. IEEE Trans. Computers 67(8): 1153-1166 (2018) - [j104]Amir Charif
First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip. IEEE Trans. Computers 67(10): 1430-1444 (2018) - [j103]Shaahin Angizi
Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1788-1801 (2018) - [j102]Ali Bozorgmehr, Mohammad Hossein Moaiyeri
Ultra-Efficient Fuzzy Min/Max Circuits Based on Carbon Nanotube FETs. IEEE Trans. Fuzzy Syst. 26(2): 1073-1078 (2018) - [j101]Zana Ghaderi
AROMa: Aging-Aware Deadlock-Free Adaptive Routing Algorithm and Online Monitoring in 3D NoCs. IEEE Trans. Parallel Distributed Syst. 29(4): 772-788 (2018) - [c121]Min Soo Kim, Alberto A. Del Barrio
Low-power implementation of Mitchell's approximate logarithmic multiplication for convolutional neural networks. ASP-DAC 2018: 617-622 - [c120]Ahmad Albaqsami, Maryam S. Hosseini, Nader Bagherzadeh
HTF-MPR: A heterogeneous TensorFlow mapper targeting performance using genetic algorithms and gradient boosting regressors. DATE 2018: 331-336 - [c119]Mahdi Torabzadehkashi
CompStor: An In-storage Computation Platform for Scalable Distributed Processing. IPDPS Workshops 2018: 1260-1267 - [c118]Sahar Nikbakht Aali, Hadi Shahriar Shahhoseini
Divisible Load Scheduling of Image Processing Applications on the Heterogeneous Star Network Using a new Genetic Algorithm. PDP 2018: 77-84 - [c117]Luis German Garcia Morales, Jose Edinson Aedo Cobo, Nader Bagherzadeh
Simulation-Based Evaluation Strategy for Task Mapping Approaches in WNoC Platforms. PDP 2018: 622-626 - 2017
- [j100]Mahya Sam Daliri
A new approach for designing compressors with a new hardware-friendly mathematical method for multi-input XOR gates. IET Circuits Devices Syst. 11(1): 46-57 (2017) - [j99]Sepehr Tabrizchi
Method for designing ternary adder cells based on CNFETs. IET Circuits Devices Syst. 11(5): 465-470 (2017) - [j98]Mahya Sam Daliri
High-performance ternary operators for scrambling. Integr. 59: 1-9 (2017) - [j97]Zahra Rouhani, Shaahin Angizi
Towards Approximate Computing with Quantum-Dot Cellular Automata. J. Low Power Electron. 13(1): 29-35 (2017) - [j96]Milad Bagherian Khosroshahy
Quantum-dot cellular automata circuits with reduced external fixed inputs. Microprocess. Microsystems 50: 154-163 (2017) - [j95]Reza Faghih Mirzaee, Mahya Sam Daliri, Keivan Navi, Nader Bagherzadeh:
A Single Parity-Check Digit for One Trit Error Detection in Ternary Communication Systems: Gate-Level and Transistor-Level Designs. J. Multiple Valued Log. Soft Comput. 29(3-4): 303-326 (2017) - [j94]Freek Verbeek
Deadlock Verification of Cache Coherence Protocols and Communication Fabrics. IEEE Trans. Computers 66(2): 272-284 (2017) - [j93]Zana Ghaderi
SENSIBle: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs. IEEE Trans. Computers 66(5): 919-926 (2017) - [j92]Hongzhi Zhao, Nader Bagherzadeh
A General Fault-Tolerant Minimal Routing for Mesh Architectures. IEEE Trans. Computers 66(7): 1240-1246 (2017) - [c116]Zana Ghaderi, Ayed Alqahtani, Nader Bagherzadeh
Online monitoring and adaptive routing for aging mitigation in NoCs. DATE 2017: 67-72 - 2016
- [j91]Hamid Sarbazi-Azad, Nader Bagherzadeh
Introduction to the Special Section on On-chip parallel and network-based systems. Comput. Electr. Eng. 51: 118-120 (2016) - [j90]Fazel Sharifi, Atiyeh Panahi, Hojjat Sharifi, Keivan Navi, Nader Bagherzadeh
Design of quaternary 4-2 and 5-2 compressors for nanotechnology. Comput. Electr. Eng. 56: 64-74 (2016) - [j89]Mohammad Hossein Moaiyeri
An Efficient Analog-to-Digital Converter Based on Carbon Nanotube FETs. J. Low Power Electron. 12(2): 150-157 (2016) - [j88]Mahya Sam Daliri
Ternary cyclic redundancy check by a new hardware-friendly ternary operator. Microelectron. J. 54: 126-137 (2016) - [j87]Pooria M. Yaghini, Ashkan Eghbal
Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs. IEEE Trans. Computers 65(3): 693-705 (2016) - [j86]Hesam Shabani, Arman Roohi, Akram Reza
Loss-Aware Switch Design and Non-Blocking Detection Algorithm for Intra-Chip Scale Photonic Interconnection Networks. IEEE Trans. Computers 65(6): 1789-1801 (2016) - [j85]Ronak Salamat, Misagh Khayambashi, Masoumeh Ebrahimi, Nader Bagherzadeh
A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs. IEEE Trans. Computers 65(11): 3265-3279 (2016) - [j84]Michael Opoku Agyeman
Performance and Energy Aware Inhomogeneous 3D Networks-on-Chip Architecture Generation. IEEE Trans. Parallel Distributed Syst. 27(6): 1756-1769 (2016) - [c115]Freek Verbeek, Pooria M. Yaghini, Ashkan Eghbal, Nader Bagherzadeh:
ADVOCAT: Automated deadlock verification for on-chip cache coherence and interconnects. DATE 2016: 1640-1645 - [c114]Ronak Salamat, Masoumeh Ebrahimi, Nader Bagherzadeh
CoBRA: Low cost compensation of TSV failures in 3D-NoC. DFT 2016: 115-120 - 2015
- [j83]Masoud Daneshtalab
Special issue on on-chip parallel and network-based systems. Computing 97(6): 539-541 (2015) - [j82]Ayhan Demiriz
Using constraint programming for the design of network-on-chip architectures. Computing 97(6): 579-592 (2015) - [j81]Masoomeh Jasemi, Reza Faghih Mirzaee
Voltage mirror circuit by carbon nanotube field effect transistors for mirroring dynamic random access memories in multiple-valued logic and fuzzy logic. IET Circuits Devices Syst. 9(5): 343-352 (2015) - [j80]Masoud Daneshtalab
On-chip parallel and network-based systems. Integr. 50: 137-138 (2015) - [j79]Pooria M. Yaghini, Ashkan Eghbal, Nader Bagherzadeh
On the design of hybrid routing mechanism for mesh-based network-on-chip. Integr. 50: 183-192 (2015) - [j78]Shaahin Angizi
Design and Verification of New n-Bit Quantum-Dot Synchronous Counters Using Majority Function-Based JK Flip-Flops. J. Circuits Syst. Comput. 24(10): 1550153:1-1550153:17 (2015) - [j77]Misagh Khayambashi, Pooria M. Yaghini, Ashkan Eghbal, Nader Bagherzadeh
Analytical Reliability Analysis of 3D NoC under TSV Failure. ACM J. Emerg. Technol. Comput. Syst. 11(4): 43:1-43:16 (2015) - [j76]Shaahin Angizi
An Ultra-High Speed and Low Complexity Quantum-Dot Cellular Automata Full Adder. J. Low Power Electron. 11(2): 173-180 (2015) - [j75]Shaahin Angizi
Designing quantum-dot cellular automata counters with energy consumption analysis. Microprocess. Microsystems 39(7): 512-520 (2015) - [j74]Fazel Sharifi, Mohammad Hossein Moaiyeri
Robust and energy-efficient carbon nanotube FET-based MVL gates: A novel design approach. Microelectron. J. 46(12): 1333-1342 (2015) - [j73]Ashkan Eghbal, Pooria M. Yaghini
Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip. IEEE Trans. Computers 64(12): 3591-3604 (2015) - [j72]Hamid Sarbazi-Azad, Nader Bagherzadeh
Advances in multicore systems architectures. J. Supercomput. 71(8): 2783-2786 (2015) - [j71]Wen-Hsiang Hu, Chifeng Wang, Nader Bagherzadeh
Design and analysis of a mesh-based wireless network-on-chip. J. Supercomput. 71(8): 2830-2846 (2015) - [j70]Pooria M. Yaghini, Ashkan Eghbal, Misagh Khayambashi, Nader Bagherzadeh
Coupling Mitigation in 3-D Multiple-Stacked Devices. IEEE Trans. Very Large Scale Integr. Syst. 23(12): 2931-2944 (2015) - [c113]Pooria M. Yaghini, Ashkan Eghbal, Siavash S. Yazdi, Nader Bagherzadeh
Accurate System-level TSV-to-TSV Capacitive Coupling Fault Model for 3D-NoC. NOCS 2015: 3:1-3:8 - [c112]Ronak Salamat, Masoumeh Ebrahimi, Nader Bagherzadeh
An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip. PDP 2015: 392-395 - [c111]Ashkan Eghbal, Pooria M. Yaghini, Nader Bagherzadeh
Capacitive Coupling Mitigation for TSV-based 3D ICs. VTS 2015: 1-6 - 2014
- [j69]Ayhan Demiriz
Voltage island based heterogeneous NoC design through constraint programming. Comput. Electr. Eng. 40(8): 307-316 (2014) - [j68]Shaahin Angizi
Novel Robust Single Layer Wire Crossing Approach for Exclusive OR Sum of Products Logic Design with Quantum-Dot Cellular Automata. J. Low Power Electron. 10(2): 259-271 (2014) - [j67]Chifeng Wang, Nader Bagherzadeh
Design and evaluation of a high throughput QoS-aware and congestion-aware router architecture for Network-on-Chip. Microprocess. Microsystems 38(4): 304-315 (2014) - [j66]Alberto A. Del Barrio
Ultra-low-power adder stage design for exascale floating point units. ACM Trans. Embed. Comput. Syst. 13(3s): 105:1-105:24 (2014) - [j65]Reza Faghih Mirzaee
High-Efficient Circuits for Ternary Addition. VLSI Design 2014: 534587:1-534587:15 (2014) - [c110]Ashkan Eghbal, Pooria M. Yaghini, Siavash S. Yazdi, Nader Bagherzadeh
TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip. DFT 2014: 92-97 - [c109]Pooria M. Yaghini, Ashkan Eghbal, Nader Bagherzadeh
A GALS Router for Asynchronous Network-on-Chip. MES 2014: 52-55 - 2013
- [j64]Sanaz Azampanah, Ahmad Khademzadeh, Nader Bagherzadeh
Contention-aware selection strategy for application-specific network-on-chip. IET Comput. Digit. Tech. 7(3) (2013) - [j63]Hamid Sarbazi-Azad, Nader Bagherzadeh
Multicore computing systems: Architecture, programming tools, and applications. J. Comput. Syst. Sci. 79(4): 403-405 (2013) - [j62]Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh
Scalable load balancing congestion-aware Network-on-Chip router architecture. J. Comput. Syst. Sci. 79(4): 421-439 (2013) - [j61]Freddy Bolanos, Fredy Rivera, Jose Edison Aedo, Nader Bagherzadeh
From UML specifications to mapping and scheduling of tasks into a NoC, with reliability considerations. J. Syst. Archit. 59(7): 429-440 (2013) - [j60]Xiaohang Wang, Mei Yang, Yingtao Jiang, Maurizio Palesi, Peng Liu, Terrence S. T. Mak, Nader Bagherzadeh
Efficient multicast schemes for 3-D Networks-on-Chip. J. Syst. Archit. 59(9): 693-708 (2013) - [c108]Ayhan Demiriz
On heterogeneous network-on-chip design based on constraint programming. NoCArc@MICRO 2013: 29-34 - [c107]Ayhan Demiriz
CPNoC: On Using Constraint Programming in Design of Network-on-Chip Architecture. PDP 2013: 486-493 - [c106]Azadeh Eskandari, Ahmad Khademzadeh, Nader Bagherzadeh
Quality of Service Optimization for Network-on-Chip Using Bandwidth-Constraint Mapping Algorithm. PDP 2013: 504-508 - 2012
- [j59]W.-H. Hu, C.-Y. Chen, Jun Ho Bahn, Nader Bagherzadeh
Parallel low-density parity check decoding on a network-on-chip-based multiprocessor platform. IET Comput. Digit. Tech. 6(2): 86-94 (2012) - [j58]Abdulaziz Alhussien, Chifeng Wang, Nader Bagherzadeh
Design and evaluation of a high throughput robust router for network-on-chip. IET Comput. Digit. Tech. 6(3): 173-179 (2012) - [j57]Chifeng Wang, Nader Bagherzadeh
High-throughput differentiated service provision router architecture for wireless network-on-chip. Int. J. High Perform. Syst. Archit. 4(1): 38-56 (2012) - [j56]Freddy Bolanos, Jose Edison Aedo, Fredy Rivera, Nader Bagherzadeh:
Mapping and Scheduling in Heterogeneous NoC through Population-Based Incremental Learning. J. Univers. Comput. Sci. 18(7): 901-916 (2012) - [j55]Hamid Sarbazi-Azad, Nader Bagherzadeh
Editorial notes: Special issue on on-chip parallel and network-based systems. Microprocess. Microsystems 36(7): 529-530 (2012) - [j54]Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh
A load-balanced congestion-aware wireless network-on-chip design for multi-core platforms. Microprocess. Microsystems 36(7): 555-570 (2012) - [j53]Akira Hatanaka, Nader Bagherzadeh
A software pipelining algorithm of streaming applications with low buffer requirements. Sci. Iran. 19(3): 627-634 (2012) - [c105]Chifeng Wang, Nader Bagherzadeh
Design and Evaluation of a High Throughput QoS-Aware and Congestion-Aware Router Architecture for Network-on-Chip. PDP 2012: 457-464 - [c104]Wen-Hsiang Hu, Chifeng Wang, Nader Bagherzadeh
Design and Analysis of a Mesh-based Wireless Network-on-Chip. PDP 2012: 483-490 - [c103]Sanaz Azampanah, Ahmad Khademzadeh, Nader Bagherzadeh
LATEX: New Selection Policy for Adaptive Routing in Application-Specific NoC. PDP 2012: 515-519 - [c102]Abdulaziz Alhussien, Nader Bagherzadeh, Freek Verbeek, Bernard van Gastel, Julien Schmaltz:
A formally verified deadlock-free routing function in a fault-tolerant NoC architecture. SBCCI 2012: 1-6 - 2011
- [j52]Akira Hatanaka, Nader Bagherzadeh
A scheduling approach for distributed resource architectures with scarce communication resources. Int. J. High Perform. Syst. Archit. 3(1): 12-22 (2011) - [j51]Nader Bagherzadeh
Special issue on: On-chip parallel and network-based systems. J. Syst. Archit. 57(1): 1-3 (2011) - [j50]Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader Bagherzadeh
Area and power-efficient innovative congestion-aware Network-on-Chip architecture. J. Syst. Archit. 57(1): 24-38 (2011) - [c101]Chifeng Wang, Wen-Hsiang Hu, Nader Bagherzadeh
A Wireless Network-on-Chip Design for Multicore Platforms. PDP 2011: 409-416 - [c100]Jungsook Yang, Chuny Chun, Nader Bagherzadeh
Load Balancing for Data-Parallel Applications on Network-on-Chip Enabled Multi-processor Platform. PDP 2011: 439-446 - 2010
- [j49]Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Jungsook Yang, Nader Bagherzadeh
Parallel processing for block ciphers on a fault tolerant networked processor array. Int. J. High Perform. Syst. Archit. 2(3/4): 156-167 (2010) - [c99]Frank Penczek, Stephan Herhut, Sven-Bodo Scholz
Message Driven Programming with S-Net: Methodology and Performance. ICPP Workshops 2010: 405-412 - [c98]Abdulaziz Alhussien, Chifeng Wang, Nader Bagherzadeh
A scalable delay insensitive asynchronous NoC with adaptive routing. ICT 2010: 995-1002 - [c97]Chifeng Wang, Wen-Hsiang Hu, Seung Eun Lee, Nader Bagherzadeh
Area and Power-efficient Innovative Network-on-Chip Architecurte. PDP 2010: 533-539
2000 – 2009
- 2009
- [j48]Radha Guha, Nader Bagherzadeh
Resource management and task partitioning and scheduling on a run-time reconfigurable embedded system. Comput. Electr. Eng. 35(2): 258-285 (2009) - [j47]Seung Eun Lee, Nader Bagherzadeh
A high level power model for Network-on-Chip (NoC) router. Comput. Electr. Eng. 35(6): 837-845 (2009) - [j46]Faruk Bagci, Florian Kluge, Theo Ungerer, Nader Bagherzadeh
Optimisations for LocSens - an indoor location tracking system using wireless sensors. Int. J. Sens. Networks 6(3/4): 157-166 (2009) - [j45]Seung Eun Lee, Nader Bagherzadeh
A variable frequency link for a power-aware network-on-chip (NoC). Integr. 42(4): 479-485 (2009) - [j44]Jun Ho Bahn, Jungsook Yang, Wen-Hsiang Hu, Nader Bagherzadeh
Parallel FFT Algorithms on Network-on-Chips. J. Circuits Syst. Comput. 18(2): 255-269 (2009) - [j43]Nader Bagherzadeh
Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip. J. Circuits Syst. Comput. 18(2): 283-294 (2009) - [j42]Marcos Sánchez-Élez
A framework for low energy data management in reconfigurable multi-context architectures. J. Syst. Archit. 55(2): 127-139 (2009) - [c96]Faruk Bagci, Julian Wolf, Theo Ungerer, Nader Bagherzadeh:
Mobile Agents for Wireless Sensor Networks. ICWN 2009: 502-508 - [c95]Seung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra S. Yavatkar, Shih-Lien Lu, Nader Bagherzadeh
Low power adaptive pipeline based on instruction isolation. ISQED 2009: 788-793 - [c94]Yoon Seok Yang, Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
Parallel and Pipeline Processing for Block Cipher Algorithms on a Network-on-Chip. ITNG 2009: 849-854 - [c93]Akira Hatanaka, Nader Bagherzadeh
Scheduling Techniques for Multi-Core Architectures. ITNG 2009: 865-870 - [c92]Wen-Hsiang Hu, Jun Ho Bahn, Nader Bagherzadeh
Parallel LDPC Decoding on a Network-on-Chip Based Multiprocessor Platform. SBAC-PAD 2009: 35-40 - 2008
- [j41]Jun Ho Bahn, Nader Bagherzadeh
Design of simulation and analytical models for a 2D-meshed asymmetric adaptive router. IET Comput. Digit. Tech. 2(1): 63-73 (2008) - [j40]Fredy Rivera, Marcos Sánchez-Élez
Scheduling methodology for conditional execution of kernels onto multicontext reconfigurable architectures. IET Comput. Digit. Tech. 2(3): 199-213 (2008) - [j39]Nozar Tabrizi, Nader Bagherzadeh
An ASIC design and formal analysis of a novel pipelined and parallel sorting accelerator. Integr. 41(1): 65-75 (2008) - [j38]Jun Ho Bahn, Seung Eun Lee, Yoon Seok Yang, Jungsook Yang, Nader Bagherzadeh
On Design and Application Mapping of a Network-on-Chip(NoC) Architecture. Parallel Process. Lett. 18(2): 239-255 (2008) - [c91]Seung Eun Lee, Jun Ho Bahn, Yoon Seok Yang, Nader Bagherzadeh
A Generic Network Interface Architecture for a Networked Processor Array (NePA). ARCS 2008: 247-260 - [c90]Hala Elsadek, Hesham Eldeeb, Haytham Abdallah, Maha Eldesouky, Nader Bagherzadeh:
Specific Absorption Rate Calculation using Parallel 3D Finite Difference Time Domain Technique. Communications in Computing 2008: 153-159 - [c89]Jun Ho Bahn, Nader Bagherzadeh
Efficient Parallel Buffer Structure and Its Management Scheme for a Robust Network-on-Chip (NoC) Architecture. CSICC 2008: 98-105 - [c88]Faruk Bagci, Florian Kluge, Nader Bagherzadeh
LocSens - An Indoor Location Tracking System using Wireless Sensors. ICCCN 2008: 887-891 - [c87]Faruk Bagci, Theo Ungerer, Nader Bagherzadeh:
ESTR - Energy Saving Token Ring Protocol for Wireless Sensor Networks. ICWN 2008: 3-9 - [c86]Wolfgang Trumler, Sebastian Schlingmann, Theo Ungerer, Jun Ho Bahn, Nader Bagherzadeh
Self-optimized Routing in a Network on-a-Chip. BICC 2008: 199-212 - [c85]Jun Ho Bahn, Jungsook Yang, Nader Bagherzadeh
Parallel FFT Algorithms on Network-on-Chips. ITNG 2008: 1087-1093 - [c84]Nader Bagherzadeh
Performance Impact of Task-to-Task Communication Protocol in Network-on-Chip. ITNG 2008: 1101-1106 - [c83]Afshin Niktash, Hooman Parizi, Amir Hosein Kamalizad, Nader Bagherzadeh:
RECFEC: A Reconfigurable FEC Processor for Viterbi, Turbo, Reed-Solomon and LDPC Coding. WCNC 2008: 605-610 - 2007
- [j37]Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
Design of a router for network-on-chip. Int. J. High Perform. Syst. Archit. 1(2): 98-105 (2007) - [j36]Bita Gorjiara, Nader Bagherzadeh
Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling. ACM Trans. Design Autom. Electr. Syst. 12(4): 39 (2007) - [c82]Afshin Niktash, Hooman Parizi, Nader Bagherzadeh:
A Reconfigurable Processor for Forward Error Correction. ARCS 2007: 1-13 - [c81]Bita Gorjiara, Nader Bagherzadeh
Integrating Power Management into Distributed Real-time Systems at Very Low Implementation Cost. ASP-DAC 2007: 872-877 - [c80]Fredy Rivera, Marcos Sánchez-Élez, Nader Bagherzadeh:
Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures. ERSA 2007: 85-91 - [c79]Akira Hatanaka, Nader Bagherzadeh
A Modulo Scheduling Algorithm for a Coarse-Grain Reconfigurable Array Template. IPDPS 2007: 1-8 - [c78]Afshin Niktash, Hooman Parizi, Nader Bagherzadeh:
Application of a Heterogeneous Reconfigurable Architecture to OFDM Wireless Systems. ISCAS 2007: 2586-2589 - [c77]Jun Ho Bahn, Seung Eun Lee, Nader Bagherzadeh
On Design and Analysis of a Feasible Network-on-Chip (NoC) Architecture. ITNG 2007: 1033-1038 - [c76]Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP). SBAC-PAD 2007: 211-218 - 2006
- [c75]Seung Eun Lee, Nader Bagherzadeh
Increasing the throughput of an adaptive router in network-on-chip (NoC). CODES+ISSS 2006: 82-87 - [c74]Javier Davila, Alfonso de Torres, Jose Manuel Sanchez, Marcos Sánchez-Élez, Nader Bagherzadeh, Fredy Rivera:
Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys). DATE Designers' Forum 2006: 52-57 - [c73]Fredy Rivera, Marcos Sánchez-Élez
Configuration Scheduling for Conditional Branch Execution Onto Multi-Context Reconfigurable Architectures. FPL 2006: 1-8 - [c72]Hooman Parizi, Afshin Niktash, Amir Hosein Kamalizad, Nader Bagherzadeh
A Reconfigurable Architecture for Wireless Communication Systems. ITNG 2006: 250-255 - [c71]Afshin Niktash, Hooman Parizi, Nader Bagherzadeh
A Multi-Standard Viterbi Decoder for Mobile Applications Using a Reconfigurable Architecture. VTC Fall 2006: 1-5 - 2005
- [c70]Amir Hosein Kamalizad, Nozar Tabrizi, Nader Bagherzadeh
A Programmable DSP Architecture for Wireless Communication Systems. ASAP 2005: 231-238 - [c69]Fredy Rivera, Milagros Fernández, Nader Bagherzadeh
An Approach to Execute Conditional Branches onto SIMD Multi-Context Reconfigurable Architectures. DSD 2005: 396-402 - [c68]Fredy Rivera, Marcos Sánchez-Élez
Low Power Data Prefetch for 3D Image Applications on Coarse-Grain Reconfigurable Architectures. IPDPS 2005 - [e1]Nader Bagherzadeh, Mateo Valero, Alex Ramírez:
Proceedings of the Second Conference on Computing Frontiers, 2005, Ischia, Italy, May 4-6, 2005. ACM 2005, ISBN 1-59593-019-1 [contents] - 2004
- [c67]Bita Gorjiara, Pai H. Chou, Nader Bagherzadeh, Mehrdad Reshadi, David W. Jensen:
Fast and efficient voltage scheduling by evolutionary slack distribution. ASP-DAC 2004: 659-662 - [c66]Nozar Tabrizi, Nader Bagherzadeh, Amir Hosein Kamalizad, Haitao Du:
MaRS: a macro-pipelined reconfigurable system. Conf. Computing Frontiers 2004: 343-349 - [c65]Fredy Rivera, Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Nader Bagherzadeh:
Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures. CODES+ISSS 2004: 30-35 - [c64]Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou:
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes. ISLPED 2004: 381-386 - [c63]Amir Hosein Kamalizad, Richard Plettner, Chengzhi Pan, Nader Bagherzadeh:
Fast parallel soft Viterbi decoder mapping on a reconfigurable DSP platform. SoCC 2004: 3-6 - 2003
- [j35]Marcos Sánchez-Élez
Algorithm optimizations and mapping scheme for interactive ray tracing on a reconfigurable architecture. Comput. Graph. 27(5): 701-713 (2003) - [j34]Girish Venkataramani, Walid A. Najjar
Automatic compilation to a coarse-grained reconfigurable system-opn-chip. ACM Trans. Embed. Comput. Syst. 2(4): 560-589 (2003) - [c62]Robert Reuss, Jose L. Muñoz, Toshiaki Miyazaki, Nader Bagherzadeh, Prith Banerjee, Brad L. Hutchings, Brian Schott:
Adaptive computing: what can it do, where can it go? ASP-DAC 2003: 463 - [c61]Haitao Du, Marcos Sánchez-Élez, Nozar Tabrizi, Nader Bagherzadeh, Manuel Lois Anido, Milagros Fernández:
Interactive ray tracing on reconfigurable SIMD MorphoSys. ASP-DAC 2003: 471-476 - [c60]Dexin Li, Pai H. Chou, Nader Bagherzadeh:
Topology selection for energy minimization in embedded networks. ASP-DAC 2003: 693-696 - [c59]Arezou Koohi, Nader Bagherzadeh, Chengzi Pan:
A fast parallel reed-solomon decoder on a reconfigurable architecture. CODES+ISSS 2003: 59-64 - [c58]Marcos Sánchez-Élez, Milagros Fernández, Manuel L. Anido, Haitao Du, Nader Bagherzadeh, Román Hermida:
Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures. DATE 2003: 10036-10043 - [c57]Chengzhi Pan, Nader Bagherzadeh, Amir Hosein Kamalizad, Arezou Koohi:
Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver. DATE 2003: 10468-10475 - [c56]Haitao Du, Marcos Sánchez-Élez
Interactive Ray Tracing on Reconfigurable SIMD MorphoSys. DATE 2003: 20144-20149 - [c55]Alexander Paar, Haitao Du, Nader Bagherzadeh:
A Component Oriented Simulator for HW/SW Co-Designs. ESTIMedia 2003: 79-86 - [c54]Miguel Sainz, Antonio Susín, A. Cervantes, Nader Bagherzadeh:
Persepolis: Recovering history with a handheld camera. Eurographics (Posters) 2003 - [c53]Miguel Sainz, Antonio Susín, Nader Bagherzadeh:
Camera calibration of long image sequences with the presence of occlusions. ICIP (1) 2003: 317-320 - [c52]Amir Hosein Kamalizad, Chengzhi Pan, Nader Bagherzadeh:
Fast Parallel FFT on a Reconfigurable Computation Platform. SBAC-PAD 2003: 254-259 - [p1]Haitao Du, Marcos Sánchez-Élez, Nozar Tabrizi, Nader Bagherzadeh, Manuel L. Anido, Milagros Fernández:
Interactive Ray Tracing on Reconfigurable SIMD Morphosys. Embedded Software for SoC 2003: 151-163 - 2002
- [j33]Pai H. Chou, Jinfeng Liu, Dexin Li, Nader Bagherzadeh:
IMPACCT: Methodology and Tools for Power-Aware Embedded Systems. Des. Autom. Embed. Syst. 7(3): 205-232 (2002) - [c51]Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh:
Communication speed selection for embedded systems with networked voltage-scalable processors. CODES 2002: 169-174 - [c50]Marcos Sánchez-Élez
A Complete Data Scheduler for Multi-Context Reconfigurable Architectures. DATE 2002: 547-552 - [c49]Manuel Lois Anido, Alexander Paar, Nader Bagherzadeh:
Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches. DSD 2002: 148-155 - [c48]Alexander Paar, Manuel L. Anido, Nader Bagherzadeh:
A Novel Predication Scheme for a SIMD System-on-Chip. Euro-Par 2002: 834-843 - [c47]Hooman Parizi, Afshin Niktash, Nader Bagherzadeh, Fadi J. Kurdahi:
MorphoSys: A Coarse Grain Reconfigurable Architecture for Multimedia Applications (Research Note). Euro-Par 2002: 844-848 - [c46]Nader Bagherzadeh, Pai H. Chou, Jinfeng Liu:
Combined Functional Partitioning and Communication Speed Selection for Networked Voltage-Scalable Processors. ISSS 2002: 14-19 - [c45]Miguel Sainz, Nader Bagherzadeh, Antonio Susín:
Recovering 3D Metric Structure and Motion from Multiple Uncalibrated Cameras. ITCC 2002: 268-273 - [c44]Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh:
Power-Aware Task Motion for Enhancing Dynamic Range of Embedded Systems with Renewable Energy Sources. PACS 2002: 84-98 - [c43]Manuel L. Anido, Nader Bagherzadeh, Nozar Tabrizi, Haitao Du, Marcos Sánchez-Élez
Interactive Ray Tracing Using a SIMD Reconfigurable Architecture. SBAC-PAD 2002: 20-28 - [c42]Manuel Lois Anido, Alexander Paar, Nader Bagherzadeh:
A Novel Method for Improving the Operation Autonomy of SIMD Processing Elements. SBCCI 2002: 49-56 - [c41]Dexin Li, Pai H. Chou, Nader Bagherzadeh:
Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems. ASP-DAC/VLSI Design 2002: 697-704 - 2001
- [j32]Rafael Maestre
Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing. J. Syst. Archit. 47(3-4): 277-292 (2001) - [j31]Rafael Maestre
A formal approach to context scheduling for multicontext reconfigurable architectures. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 173-185 (2001) - [j30]Rafael Maestre
A framework for reconfigurable computing: task scheduling and context management. IEEE Trans. Very Large Scale Integr. Syst. 9(6): 858-873 (2001) - [c40]Girish Venkataramani, Walid A. Najjar
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. CASES 2001: 116-125 - [c39]Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi:
A constraint-based application model and scheduling techniques for power-aware systems. CODES 2001: 153-158 - [c38]Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh, Fadi J. Kurdahi:
Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems. DAC 2001: 840-845 - [c37]Marcos Sánchez-Élez
A data scheduler for multi-context reconfigurable architectures. ISSS 2001: 177-182 - [c36]Mohamed Ahamed Mead, Hesham Eldeeb, Salwa M. Nassar, Nader Bagherzadeh:
Design and implementation of Automatic Parallel Detection Layer. SMC 2001: 2371-2376 - 2000
- [j29]Fadi J. Kurdahi, Nader Bagherzadeh, Peter Athanas, Jose L. Muñoz:
Guest Editors' Introduction: Configurable Computing. IEEE Des. Test Comput. 17(1): 17-19 (2000) - [j28]Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi
MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications. IEEE Trans. Computers 49(5): 465-481 (2000) - [j27]Ming-Hau Lee, Hartej Singh, Guangming Lu, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho, Vladimir Castro Alves:
Design and Implementation of the MorphoSys Reconfigurable Computing Processor. J. VLSI Signal Process. 24(2-3): 147-164 (2000) - [c35]Hartej Singh, Guangming Lu, Eliseu M. Chaves Filho, Rafael Maestre, Ming-Hau Lee, Fadi J. Kurdahi, Nader Bagherzadeh:
MorphoSys: case study of a reconfigurable computing system targeting multimedia applications. DAC 2000: 573-578 - [c34]Rafael Maestre
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. FCCM 2000: 297-298 - [c33]Rafael Maestre, Milagros Fernández, Román Hermida, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh:
Optimal vs. Heuristic Approaches to Context Scheduling for Multi-Context Reconfigurable Architectures. ICCD 2000: 575-576 - [c32]Rafael Maestre
Configuration Management in Multi-Context Reconfigurable Systems for Simultaneous Performance and Power Optimization. ISSS 2000: 107-114
1990 – 1999
- 1999
- [c31]Rafael Maestre
Kernel Scheduling in Reconfigurable Computing. DATE 1999: 90-96 - [c30]Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi
The MorphoSys Dynamically Reconfigurable System-on-Chip. Evolvable Hardware 1999: 152-160 - [c29]Guangming Lu, Hartej Singh, Ming-Hau Lee, Nader Bagherzadeh, Fadi J. Kurdahi, Eliseu M. Chaves Filho:
The MorphoSys Parallel Reconfigurable System. Euro-Par 1999: 727-734 - [c28]Guangming Lu, Ming-Hau Lee, Hartej Singh, Nader Bagherzadeh, Fadi J. Kurdahi
MorphoSys: A Reconfigurable Processor Trageted to High Performance Image Application. IPPS/SPDP Workshops 1999: 661-669 - [c27]Rafael Maestre, Milagros Fernández, Román Hermida, Nader Bagherzadeh:
A Framework for Scheduling and Context Allocation in Reconfigurable Computing. ISSS 1999: 134-140 - 1998
- [j26]Steven Wallace, Nader Bagherzadeh:
A scalable register file architecture for superscalar processors. Microprocess. Microsystems 22(1): 49-60 (1998) - [j25]S. Shoari, Nader Bagherzadeh, D. Goodman, Thomas E. Milner, D. J. Smithies, J. Stuart Nelson:
A parallel algorithm for pulsed laser infrared tomography. Pattern Recognit. Lett. 19(5-6): 521-526 (1998) - [j24]Nader Bagherzadeh, Martin Dowd, Shahram Latifi:
Faster column operations in star networks. Telecommun. Syst. 10(1): 33-44 (1998) - [j23]Marcelo M. de Azevedo, Nader Bagherzadeh, Shahram Latifi:
Low Expansion Packings and Embeddings of Hypercubes into Star Graphs: A Performance-Oriented Approach. IEEE Trans. Parallel Distributed Syst. 9(3): 261-274 (1998) - [j22]Steven Wallace, Nader Bagherzadeh:
Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors. IEEE Trans. Parallel Distributed Syst. 9(6): 570-578 (1998) - [c26]Hartej Singh, Ming-Hau Lee, Guangming Lu, Fadi J. Kurdahi, Nader Bagherzadeh:
MorphoSys: A Reconfigurable Architecture for Multimedia Applications. SBCCI 1998: 134-140 - 1997
- [j21]Shahram Latifi, Nader Bagherzadeh:
On Embedding Rings into a Star-Related Network. Inf. Sci. 99(1-2): 21-35 (1997) - [c25]Steven Wallace, Nader Bagherzadeh:
Multiple Branch and Block Prediction. HPCA 1997: 94-103 - 1996
- [j20]Marcelo M. de Azevedo, Nader Bagherzadeh, Martin Dowd, Shahram Latifi:
Some Topological Properties of Star Connected Cycles. Inf. Process. Lett. 58(2): 81-85 (1996) - [j19]Nayla Nassif, Nader Bagherzadeh:
A Grid Embedding into the Star Graph for Image Analysis Solutions. Inf. Process. Lett. 60(5): 255-260 (1996) - [j18]Nader Bagherzadeh, Martin Dowd, Nayla Nassif:
Embedding an Arbitrary Binary Tree into the Star Graph. IEEE Trans. Computers 45(4): 475-481 (1996) - [c24]M. Loikkanen, Nader Bagherzadeh:
A fine-grain multithreading superscalar architecture. IEEE PACT 1996: 163-168 - [c23]Steven Wallace, Nader Bagherzadeh:
A scalable register file architecture for dynamically scheduled processors. IEEE PACT 1996: 179-184 - [c22]Marcelo Moraes de Azevdeo, Nader Bagherzadeh, Shahram Latifi:
Variable-Dilation Embeddings of Hypercubes into Star Graphs: Performance Metrics, Mapping Functions, and Routing. Euro-Par, Vol. I 1996: 247-252 - [c21]Steven Wallace, Nader Bagherzadeh:
Instruction Fetching Mechanisms for Superscalar Microprocessors. Euro-Par, Vol. II 1996: 747-756 - [c20]Manu Gulati, Nader Bagherzadeh:
Performance Study of a Multithreaded Superscalar Microprocessor. HPCA 1996: 291-301 - [c19]Shahram Latifi, Nader Bagherzadeh:
Hamiltonicity of the Clustered-Star Graph with Embedding Applications. PDPTA 1996: 734-744 - [c18]Marcelo M. de Azevedo, Nader Bagherzadeh, Martin Dowd, Shahram Latifi:
Average distance and routing algorithms in the star-connected cycles interconnection network. SPDP 1996: 443-452 - 1995
- [j17]Marcelo M. de Azevedo, Nader Bagherzadeh, Shahram Latifi:
Broadcasting Algorithms for the Star-Connected Cycles Interconnection Network. J. Parallel Distributed Comput. 25(2): 209-222 (1995) - [j16]Steven Wallace, Nader Bagherzadeh:
Performance issues of a superscalar microprocessor. Microprocess. Microsystems 19(4): 187-199 (1995) - [j15]Nader Bagherzadeh, Martin Dowd, Shahram Latifi:
A Well-Behaved Enumeration of Star Graphs. IEEE Trans. Parallel Distributed Syst. 6(5): 531-535 (1995) - [c17]Marcelo M. de Azevedo, Nader Bagherzadeh, Shahram Latifi:
Fault-diameter of the star-connected cycles interconnection network. HICSS (2) 1995: 469-478 - [c16]Steven Wallace, Nirav Dagli, Nader Bagherzadeh:
Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor. ICCD 1995: 96-101 - 1994
- [j14]Alireza Kavianpour, Nader Bagherzadeh:
Parallel Algorithms for Line Detection on A Pyramid Architecture. Int. J. Pattern Recognit. Artif. Intell. 8(1): 337-349 (1994) - [j13]S. Shoari, Alireza Kavianpour, Nader Bagherzadeh:
Pyramid simulation of image processing applications. Image Vis. Comput. 12(8): 523-529 (1994) - [j12]Alireza Kavianpour, S. Shoari, Nader Bagherzadeh:
A New Approach for Circle Detection on Multiprocessors. J. Parallel Distributed Comput. 20(2): 256-260 (1994) - [j11]John Lenell, Nader Bagherzadeh:
A performance comparison of several superscalar processor models with a VLIW processor. Microprocess. Microsystems 18(3): 131-139 (1994) - [j10]Shahram Latifi, Nader Bagherzadeh:
Incomplete Star: An Incrementally Scalable Network Based on the Star Graph. IEEE Trans. Parallel Distributed Syst. 5(1): 97-102 (1994) - [j9]Arthur Abnous, Nader Bagherzadeh:
Pipelining and Bypassing in a VLIW Processor. IEEE Trans. Parallel Distributed Syst. 5(6): 658-664 (1994) - [c15]Steven Wallace, Nader Bagherzadeh:
Performance Issues of a Superscalar Microprocessor. ICPP (1) 1994: 293-297 - 1993
- [j8]Alireza Kavianpour, Nader Bagherzadeh:
A Systematic Approch for Mapping Application Tasks in Hypercubes. IEEE Trans. Computers 42(6): 742-746 (1993) - [j7]Nader Bagherzadeh, Nayla Nassif, Shahram Latifi:
A Routing and Broadcasting Scheme on Faulty Star Graphs. IEEE Trans. Computers 42(11): 1398-1403 (1993) - [c14]Shahram Latifi, Marcelo M. de Azevedo, Nader Bagherzadeh:
The Star Connected Cycles: A Fixed-Degree Network for Parallel Processing. ICPP (1) 1993: 91-95 - [c13]John Lenell, Nader Bagherzadeh:
A Performance Comparison of Several Superscalar Processor Models with a VLIW Processor. IPPS 1993: 44-48 - [c12]Shahram Latifi, Nader Bagherzadeh:
The Clustered-Star Graph: A New Topology for Large Interconnection Networks. IPPS 1993: 514-518 - 1992
- [j6]Arthur Abnous, Christopher Christensen, Jeffrey Gray, John Lenell, Andrew Naylor, Nader Bagherzadeh:
Design and implementation of the 'Tiny RISC' microprocessor. Microprocess. Microsystems 16(4): 187-193 (1992) - [j5]Alireza Kavianpour, Nader Bagherzadeh:
Finding circular shapes in an image on a pyramid architecture. Pattern Recognit. Lett. 13(12): 843-848 (1992) - [c11]Shahram Latifi, Si-Qing Zheng, Nader Bagherzadeh:
Optimal Ring Embedding in Hypercubes with Faulty Links. FTCS 1992: 178-184 - [c10]Takaaki Kato, Koji Suginuma, Nader Bagherzadeh:
On Design and Performance Analysis of a Superscalar Architecture. ICPP (1) 1992: 171-178 - [c9]Nader Bagherzadeh, Kent Hawk:
Parallel Implementation of the Auction Algorithm on the Intel Hypercube. IPPS 1992: 443-447 - [c8]Arthur Abnous, Nader Bagherzadeh:
Pipelining and bypassing in a VLIW processor. ISCA 1992: 434 - [c7]Takaaki Kato, Toshihisa Ono, Nader Bagherzadeh:
Performance analysis and design methodology for a scalable superscalar architecture. MICRO 1992: 246-255 - 1991
- [j4]Nader Bagherzadeh, Seng-lai Heng, Chuan-lin Wu:
A Parallel Asynchronous Garbage Collection Algorithm for Distributed Systems. IEEE Trans. Knowl. Data Eng. 3(1): 100-107 (1991) - [c6]Arthur Abnous, Roni Potasman, Nader Bagherzadeh, Alexandru Nicolau:
A Percolation Based VLIW Architecture. ICPP (1) 1991: 144-148 - [c5]Alireza Kavianpour, Nader Bagherzadeh:
Parallel Hough Transform for Image Processing on a Pyramid Architecture. ICPP (1) 1991: 395-398 - [c4]Wei Kang Tsai, Nader Bagherzadeh, Young C. Kim:
Hypermesh: A Combined Quad Tree and Mesh Network for Parallel Processing. ICPP (1) 1991: 696-697 - [c3]Arthur Abnous, Nader Bagherzadeh:
Special Features of a VLIW Architecture. IPPS 1991: 224-227 - 1990
- [j3]Douglas M. Blough, Nader Bagherzadeh:
Near-optimal message routing and broadcasting in faulty hypercubes. Int. J. Parallel Program. 19(5): 405-423 (1990)
1980 – 1989
- 1987
- [j2]Adolfo Guzmán
Performance of symbolic applications on a parallel architecture. Int. J. Parallel Program. 16(3): 183-214 (1987) - [c2]B. Kandu, Seng-lai Heng, Chuan-lin Wu, Nader Bagherzadeh:
Network simulation of synchronous garbage collection algorithm. Simulation of Computer Networks 1987: 215-222 - 1986
- [j1]Paul A. Suhler, Nader Bagherzadeh, Miroslav Malek, Neil Iscoe:
Software Authorization Systems. IEEE Softw. 3(5): 34-41 (1986) - 1985
- [c1]Manjai Lee, Eric Fiene, Chuan-lin Wu, Geoffrey Brown, Nader Bagherzadeh:
Network Facility for a Reconfigurable Computer Architecture. ICDCS 1985: 264-271
Coauthor Index
Alberto A. Del Barrio
aka: Alberto A. Del Barrio García
aka: Alberto A. Del Barrio García
Rafael Maestre-Ferriz
aka: Rafael Maestre
aka: Rafael Maestre
Marcos Sánchez-Élez Martín
aka: Marcos Sánchez-Élez
aka: Marcos Sánchez-Élez
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-11-15 19:34 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: