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Kyu-Hyoun Kim
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2020 – today
- 2024
- [c12]Kyu-Hyoun Kim
, Mingu Kang:
Mixed-Signal Dot-Product Processor with Switched-Capacitors for Machine Learning. ICEIC 2024: 1-4 - [c11]Monodeep Kar, Joel Silberman, Swagath Venkataramani, Viji Srinivasan, Bruce M. Fleischer, Joshua Rubin, JohnDavid Lancaster, Sae Kyu Lee, Matthew Cohen, Matthew M. Ziegler, Nianzheng Cao, Sandra Woodward, Ankur Agrawal, Ching Zhou, Prasanth Chatarasi, Thomas Gooding, Michael Guillorn, Bahman Hekmatshoartabari, Philip Jacob, Radhika Jain, Shubham Jain, Jinwook Jung, Kyu-Hyoun Kim
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. ISSCC 2024: 254-256 - 2023
- [c10]Ankur Agrawal, Monodeep Kar, Kyu-Hyoun Kim
A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j8]Sae Kyu Lee
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling. IEEE J. Solid State Circuits 57(1): 182-197 (2022) - 2021
- [c9]Swagath Venkataramani, Vijayalakshmi Srinivasan, Wei Wang, Sanchari Sen, Jintao Zhang, Ankur Agrawal, Monodeep Kar, Shubham Jain, Alberto Mannari, Hoang Tran, Yulong Li, Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Marcel Schaal, Mauricio J. Serrano, Jungwook Choi, Xiao Sun
RaPiD: AI Accelerator for Ultra-low Precision Training and Inference. ISCA 2021: 153-166 - [c8]Ankur Agrawal, Sae Kyu Lee, Joel Silberman, Matthew M. Ziegler, Mingu Kang, Swagath Venkataramani, Nianzheng Cao, Bruce M. Fleischer, Michael Guillorn, Matt Cohen, Silvia M. Mueller, Jinwook Oh, Martin Lutz, Jinwook Jung, Siyu Koswatta, Ching Zhou, Vidhi Zalani, James Bonanno, Robert Casatuta, Chia-Yu Chen, Jungwook Choi, Howard Haynie, Alyssa Herbert, Radhika Jain, Monodeep Kar, Kyu-Hyoun Kim
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling. ISSCC 2021: 144-146 - [c7]Dong-Uk Lee, Bor-Doou Rong, Kyu-Hyoun Kim:
Session 25 Overview: DRAM Memory Subcommittee. ISSCC 2021: 342-343 - 2020
- [j7]Saravanan Sethuraman
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4635-4644 (2020)
2010 – 2019
- 2018
- [c6]Seokin Hong, Prashant Jayaprakash Nair, Bülent Abali, Alper Buyuktosunoglu, Kyu-Hyoun Kim
Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads. MICRO 2018: 326-338 - 2017
- [c5]Bharat Sukhwani, Thomas Roewer, Charles L. Haymes, Kyu-Hyoun Kim
Contutto: a novel FPGA-based prototyping platform enabling innovation in the memory subsystem of a server class processor. MICRO 2017: 15-26 - 2013
- [c4]Janani Mukundan, Hillery C. Hunter, Kyu-Hyoun Kim
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. ISCA 2013: 48-59
2000 – 2009
- 2009
- [c3]Kyu-Hyoun Kim
A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. ISSCC 2009: 98-99 - 2008
- [c2]Kyu-Hyoun Kim
A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator. ISSCC 2008: 458-459 - 2007
- [j6]Kyu-Hyoun Kim
A Second Order Mixed-Mode Charge Pump Scheme for Low Phase/Duty Error and Low Power Consumption. IEICE Trans. Electron. 90-C(1): 208-211 (2007) - [j5]Kyu-Hyoun Kim
An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme. IEEE J. Solid State Circuits 42(1): 193-200 (2007) - 2006
- [j4]Kyu-Hyoun Kim
A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter. IEEE J. Solid State Circuits 41(1): 127-134 (2006) - [j3]Churoo Park, Hoeju Chung, Yun-Sang Lee, Jaekwan Kim, JaeJun Lee, Moo Sung Chae, Dae-Hee Jung, Sung-Ho Choi, Seung-young Seo, Taek-Seon Park, Jun-Ho Shin, Jin-Hyung Cho, Seunghoon Lee, Ki-Whan Song, Kyu-Hyoun Kim
A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. IEEE J. Solid State Circuits 41(4): 831-838 (2006) - [c1]Kyu-Hyoun Kim
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. ISSCC 2006: 527-536
1990 – 1999
- 1999
- [j2]Dong-Ho Shin, Young-Min Lee, Kyu-Hyoun Kim
Low-power dynamic termination scheme using NMOS diode clamping. IEEE J. Solid State Circuits 34(8): 1171-1175 (1999) - 1998
- [j1]Kyu-Hyoun Kim
An 8-bit-resolution, 360-μs write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS). IEEE J. Solid State Circuits 33(11): 1758-1762 (1998)
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