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Shujiang Ji
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2020 – today
- 2024
- [j3]Hao Xu
, Shujiang Ji
Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur. IEEE Trans. Circuits Syst. I Regul. Pap. 71(8): 3597-3607 (2024) - 2023
- [j2]Yizhuo Wang, Jiahe Shi
Analysis and Design of a Dual-Mode VCO With Inherent Mode Compensation Enabling a 7.9-14.3-GHz 85-fs-rms Jitter PLL. IEEE J. Solid State Circuits 58(8): 2252-2266 (2023) - 2022
- [j1]Kuanfeng Tang
A Highly Integrated Passive Wireless Sensing System With Synchronized Data Streaming of Multiple Tags. IEEE Internet Things J. 9(17): 15525-15537 (2022) - 2021
- [c3]Yizhuo Wang, Tenghao Zou, Bowen Chen, Shujiang Ji, Chao Zhang, Na Yan:
A 7.9-14.3GHz -243.3dB FoMT Sub-Sampling PLL with Transformer-Based Dual-Mode VCO in 40nm CMOS. A-SSCC 2021: 1-3 - [c2]Kuanfeng Tang
A novel method to improve the subcarrier frequency accuracy for UHF RFID sensing system. RFID 2021: 1-6 - 2020
- [c1]Shujiang Ji, Yuxiao Zhao, Wenjie Xu, Na Yan, Hao Min:
A Novel Charge Pump with Ultra-Low Current Mismatch and Variation for PLL. ISCAS 2020: 1-4
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