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Carlos Carreras
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2010 – 2019
- 2019
- [j19]Roberto Sierra, Carlos Carreras
, Gabriel Caffarena
Witelo: Automated generation and timing characterization of distributed-control macroblocks for high-performance FPGA designs. Integr. 68: 1-11 (2019) - [c30]Roberto Sierra, Filippo Mangani, Carlos Carreras
High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing. FPL 2019: 307-313 - 2018
- [c29]Roberto Sierra, Carlos Carreras
Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs. PATMOS 2018: 7-12 - 2015
- [j18]Roberto Sierra, Carlos Carreras
A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(1): 52-62 (2015) - 2014
- [j17]Pablo Barrio, Carlos Carreras
Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes. J. Syst. Archit. 60(7): 579-591 (2014) - [j16]Bojan Jovanovic, Ruzica Jevtic
Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits. IEEE Trans. Ind. Informatics 10(1): 393-398 (2014) - 2012
- [j15]Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
A reduced complexity scheme for carrier frequency synchronization in uplink 802.16e OFDMA. EURASIP J. Adv. Signal Process. 2012: 218 (2012) - [j14]Ruzica Jevtic
A complete dynamic power estimation model for data-paths in FPGA DSP designs. Integr. 45(2): 172-185 (2012) - [j13]Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
Evaluation of Rapid Prototyping solutions for a 802.16d frequency Offset estimation Scheme. J. Circuits Syst. Comput. 21(7) (2012) - [c28]Pablo Barrio, Carlos Carreras
Turning control flow graphs into function calls: Code generation for heterogeneous architectures. HPCS 2012: 559-565 - 2011
- [j12]Ruzica Jevtic
Power Measurement Methodology for FPGA Devices. IEEE Trans. Instrum. Meas. 60(1): 237-247 (2011) - [c27]Ruzica Jevtic
Power estimation of dividers implemented in FPGAs. ACM Great Lakes Symposium on VLSI 2011: 313-318 - [c26]Pablo Barrio, Carlos Carreras
Mesh traversal and sorting for efficient memory usage in scientific codes. IPCCC 2011: 1-8 - 2010
- [j11]Gabriel Caffarena
SQNR Estimation of Fixed-Point DSP Algorithms. EURASIP J. Adv. Signal Process. 2010 (2010) - [j10]Javier Gonzalez Bayon
A Multistandard Frequency Offset Synchronization Scheme for 802.11n, 802.16d, LTE, and DVB-T/H Systems. J. Comput. Networks Commun. 2010: 628657:1-628657:9 (2010) - [j9]Javier Gonzalez Bayon, Angel Fernandez Herrero, Carlos Carreras
Improved schemes for tracking residual frequency offset in DVB-T systems. IEEE Trans. Consumer Electron. 56(2): 415-422 (2010) - [j8]Ruzica Jevtic
Power Estimation of Embedded Multiplier Blocks in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 835-839 (2010) - [c25]Gabriel Caffarena, Juan A. López, Angel Fernandez Herrero, Carlos Carreras:
SQNR estimation of non-linear fixed-point algorithms. EUSIPCO 2010: 522-526 - [c24]Gabriel Caffarena, Carlos Carreras:
Precision-wise architectural synthesis of DSP circuits. EUSIPCO 2010: 562-566 - [c23]Gabriel Caffarena
Fast Fixed-Point Optimization of DSP Algorithms. VLSI-SoC (Selected Papers) 2010: 182-205 - [c22]Gabriel Caffarena
Fast fixed-point optimization of DSP algorithms. VLSI-SoC 2010: 195-200 - [c21]Gabriel Caffarena
Architectural synthesis of DSP circuits under simultaneous error and time constraints. VLSI-SoC 2010: 322-327
2000 – 2009
- 2009
- [j7]Gabriel Caffarena, Juan A. López
Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs. Int. J. Reconfigurable Comput. 2009: 703267:1-703267:14 (2009) - [c20]Slobodan Bojanic, Vukasin Pejovic, Gabriel Caffarena
Behavioural Biometrics Hardware Based on Bioinformatics Matching. CISIS 2009: 171-178 - [c19]Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras
A Practical Method for Testing High-Speed Networking Hardware Architectures. ICNS 2009: 122-130 - [c18]Ruzica Jevtic
Floorplan-based FPGA interconnect power estimation in DSP circuits. SLIP 2009: 53-60 - 2008
- [j6]Juan A. López
Fast and accurate computation of the roundoff noise of linear time-invariant systems. IET Circuits Devices Syst. 2(4): 393-408 (2008) - [c17]Ruzica Jevtic
Analytical High-Level Power Model for LUT-Based Components. PATMOS 2008: 369-378 - [c16]Gabriel Caffarena
Optimized Architectural Synthesis of Fixed-Point Datapaths. ReConFig 2008: 85-90 - [c15]Ruzica Jevtic
A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components. ReConFig 2008: 361-366 - 2007
- [j5]Gabriel Caffarena
Fpga Acceleration for DNA Sequence Alignment. J. Circuits Syst. Comput. 16(2): 245-266 (2007) - [j4]Juan A. López
Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(11): 1923-1933 (2007) - [c14]Ruzica Jevtic
Switching Activity Models for Power Estimation in FPGA Multipliers. ARC 2007: 201-213 - [c13]Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras:
A TCP/IP Fragmentation Monitoring Core For Intrusion Prevention. ERSA 2007: 227-230 - [c12]Vukasin Pejovic, Slobodan Bojanic, Carlos Carreras
Adding Value to TCP/IP Based Information exchange Security by Specialized Hardware. SECURWARE 2007: 145-150 - 2006
- [j3]Gabriel Caffarena
Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits. IEEE Trans. Circuits Syst. II Express Briefs 53-II(5): 339-343 (2006) - [c11]Gabriel Caffarena
High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs. FPL 2006: 1-4 - [c10]Gabriel Caffarena
Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources. SoC 2006: 1-4 - 2005
- [c9]Robin McDonnell, George Grimes, Ian D. Walker, Carlos Carreras:
Extension versus bending for continuum robots. ICINCO 2005: 258-265 - 2004
- [c8]Juan A. López, Gabriel Caffarena, Carlos Carreras, Octavio Nieto-Taladriz:
Analysis of limit cycles by means of affine arithmetic computer-aided tests. EUSIPCO 2004: 991-994 - [c7]Gabriel Caffarena, Angel Fernández, Carlos Carreras, Octavio Nieto-Taladriz:
Fixed-point refinement of OFDM-based adaptive equalizers: An heuristic approach. EUSIPCO 2004: 1353-1356 - [c6]Gerardo Leyva, Gabriel Caffarena
A Generator of High-Speed Floating-Point Modules. FCCM 2004: 306-307 - 2003
- [c5]Juan A. López
Fast characterization of the noise bounds derived from coefficient and signal quantization. ISCAS (4) 2003: 309-312 - 2001
- [j2]Carlos Carreras
Interval methods for fault-tree analysis in robotics. IEEE Trans. Reliab. 50(1): 3-11 (2001) - 2000
- [j1]Carlos Carreras
On interval methods applied to robot reliability quantification. Reliab. Eng. Syst. Saf. 70(3): 291-303 (2000) - [c4]Carlos Carreras
Grid-Based Histogram Arithmetic for the Probabilistic Analysis of Functions. SARA 2000: 107-123
1990 – 1999
- 1999
- [c3]Carlos Carreras
Bit-Width Selection for Data-Path Implementations. ISSS 1999: 114-121 - 1996
- [c2]Carlos Carreras
A Co-Design Methodology Based on Formal Specification and High-level Estimation. CODES 1996: 28-35 - 1994
- [c1]Carlos Carreras
Analytic Model of a Cache Only Memory Architecture. PARLE 1994: 336-350
Coauthor Index
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