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Ramchan Woo
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2010 – 2019
- 2010
- [c9]Johannes Solhusvik, Jung-Chak Ahn, Jan T. Bosiers, Boyd Fowler, Makoto Ikeda, Shoji Kawahito, Jerry Lin, Dan McGrath, Katsu Nakamura, Jun Ohta, Ramchan Woo:
High-speed image sensor technologies. ISSCC 2010: 516-517
2000 – 2009
- 2006
- [j7]Ju-Ho Sohn, Jeong-Ho Woo, Min-wuk Lee, Hyejung Kim, Ramchan Woo, Hoi-Jun Yoo:
A 155-mW 50-m vertices/s graphics processor with fixed-point programmable vertex shader for mobile applications. IEEE J. Solid State Circuits 41(5): 1081-1091 (2006) - 2005
- [j6]Ju-Ho Sohn, Yong-Ha Park, Chi Weon Yoon, Ramchan Woo, Se-Jeong Park, Hoi-Jun Yoo:
Low-power 3D graphics processors for mobile terminals. IEEE Commun. Mag. 43(12): 90-99 (2005) - [c8]Ju-Ho Sohn, Jeong-Ho Woo, Ramchan Woo, Hoi-Jun Yoo:
A fixed-point multimedia coprocessor with 50Mvertices/s programmable SIMD vertex shader for mobile applications. ESSCIRC 2005: 207-210 - 2004
- [j5]Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Hoi-Jun Yoo:
A 210-mW graphics LSI implementing full 3-D pipeline with 264 mtexels/s texturing for mobile multimedia applications. IEEE J. Solid State Circuits 39(2): 358-367 (2004) - [j4]Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, Hoi-Jun Yoo:
A low-power 3D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals. IEEE J. Solid State Circuits 39(7): 1101-1109 (2004) - [c7]Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, Hoi-Jun Yoo:
A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications. ASP-DAC 2004: 533-534 - [c6]Ju-Ho Sohn, Ramchan Woo, Hoi-Jun Yoo:
A programmable vertex shader with fixed-point SIMD datapath for low power wireless applications. Graphics Hardware 2004: 107-114 - [c5]Ramchan Woo:
3D graphics circuits for 3G multimedia terminals. SoC 2004 - 2003
- [c4]Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Hoi-Jun Yoo:
A low power 3D rendering engine with two texture units and 29Mb embedded DRAM for 3G multimedia terminals. ESSCIRC 2003: 53-56 - 2002
- [j3]Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kang-Min Lee, Tae-Hum Yang, Jin-Yong Jung, Hoi-Jun Yoo:
A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth. IEEE J. Solid State Circuits 37(5): 612-623 (2002) - [j2]Ramchan Woo, Chi Weon Yoon, Jeonghoon Kook, Se-Joong Lee, Hoi-Jun Yoo:
A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip. IEEE J. Solid State Circuits 37(10): 1352-1355 (2002) - [c3]Ju-Ho Sohn, Ramchan Woo, Hoi-Jun Yoo:
Optimization of portable system architecture for real-time 3D graphics. ISCAS (1) 2002: 769-772 - 2001
- [j1]Chi Weon Yoon, Ramchan Woo, Jeengheon Kook, Se-Joong Lee, Kangmin Lee, Hoi-Jun Yeo:
An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications. IEEE J. Solid State Circuits 36(11): 1758-1767 (2001) - [c2]Kangmin Lee, Chi Weon Yoon, Ramchan Woo, Jeong-Hun Kook, Ja-Il Koo, Tae-Sung Jung, Hoi-Jun Yoo:
A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator. ISCAS (5) 2001: 81-84 - 2000
- [c1]Ramchan Woo, Se-Joong Lee, Hoi-Jun Yoo:
A 670 ps, 64 bit dynamic low-power adder design. ISCAS 2000: 28-31
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