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Chongyun Zhang

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2024
[c5]
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  - conf/vlsit/Zhang0LC0LY24
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Chongyun Zhang, Li Wang, Zilu Liu, Fuzhan Chen, Quan Pan, Xianbo Li, C. Patrick Yue:
A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm² area in 28-nm CMOS. VLSI Technology and Circuits 2024: 1-2
2023
[c4]
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  - conf/esscirc/ChenZWPY23
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Fuzhan Chen, Chongyun Zhang, Li Wang, Quan Pan, C. Patrick Yue:
A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS. ESSCIRC 2023: 373-376
2022
[c3]
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Chongyun Zhang, Fuzhan Chen, C. Patrick Yue:
A 56-Gb/s PAM-4 Transmitter Using Silicon Photonic Microring Modulator in 40nm CMOS. MWSCAS 2022: 1-4
2021
[c2]
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Fuzhan Chen, Chongyun Zhang, Tianxin Min, Bo Xu, Quan Pan, C. Patrick Yue:
Design and Co-Simulation of QPSK and NRZ/PAM-4/PAM-8 VCSEL-Based Optical Links Utilizing an Integrated System Evaluation Engine. ASICON 2021: 1-4
[c1]
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Weimin Shi, Fuzhan Chen, Xinyi Liu, Chongyun Zhang, Zilu Liu, Tianxin Min, Bo Xu, Li Wang, Jian Kang, C. Patrick Yue:
An Integrated System Evaluation Engine for Cross-Domain Simulation and Design Optimization of High-Speed 5G Millimeter-Wave Wireless SoCs. ASICON 2021: 1-4

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