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Oskar Andersson
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2020 – today
- 2024
- [j5]Zuzana Jelcicová
, Evangelia Kasapaki, Oskar Andersson
PeakEngine: A Deterministic On-the-Fly Pruning Neural Network Accelerator for Hearing Instruments. IEEE Trans. Very Large Scale Integr. Syst. 32(1): 150-163 (2024) - 2023
- [c16]Zuzana Jelcicová
A Min-Heap-Based Accelerator for Deterministic On-the-Fly Pruning in Neural Networks. ISCAS 2023: 1-5 - 2020
- [c15]Zuzana Jelcicová
A Neural Network Engine for Resource Constrained Embedded Systems. ACSSC 2020: 125-131
2010 – 2019
- 2018
- [j4]Shahzad Asif, Oskar Andersson
65-nm CMOS low-energy RNS modular multiplier for elliptic-curve cryptography. IET Comput. Digit. Tech. 12(2): 62-67 (2018) - [j3]Babak Mohammadi
A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28-nm FD-SOI. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(4): 1257-1268 (2018) - 2017
- [c14]Farhana Sheikh
Adaptive and multi-mode baseband systems for next generation wireless communication. ACSSC 2017: 1499-1503 - 2016
- [j2]Oskar Andersson
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(6): 806-817 (2016) - [c13]Babak Mohammadi, Oskar Andersson
An area efficient single-cycle xVDD sub-Vth on-chip boost scheme in 28 nm FD-SOI. A-SSCC 2016: 229-232 - [c12]Babak Mohammadi, Oskar Andersson
A 128 kb single-bitline 8.4 fJ/bit 90MHz at 0.3V 7T sense-amplifierless SRAM in 28 nm FD-SOI. ESSCIRC 2016: 429-432 - [c11]Alen Bardizbanyan, Oskar Andersson
Logic filter cache for wide-VDD-range processors. ICECS 2016: 376-379 - [i1]Nafiseh Seyed Mazloum, Joachim Neves Rodrigues, Oskar Andersson, Anders Nejdel, Ove Edfors:
Improving practical sensitivity of energy optimized wake-up receivers: proof of concept in 65nm CMOS. CoRR abs/1605.00113 (2016) - 2015
- [j1]Oskar Andersson
A 290 mV Sub-V𝕋 ASIC for Real-Time Atrial Fibrillation Detection. IEEE Trans. Biomed. Circuits Syst. 9(3): 377-386 (2015) - [c10]Oskar Andersson
A 400 mV atrial fibrillation detector with 0.56 pJ/operation in 65nm CMOS. ISCAS 2015: 2628-2631 - [c9]Farhana Sheikh
Reconfıgurable and selectively-adaptive signal processing for multi-mode wireless communication. SiPS 2015: 1-6 - 2014
- [c8]Oskar Andersson
A 35 fJ/bit-access sub-VT memory using a dual-bit area-optimized standard-cell in 65 nm CMOS. ESSCIRC 2014: 243-246 - 2013
- [c7]Oskar Andersson
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS. ESSCIRC 2013: 197-200 - [c6]Christoph Thomas Muller, Steffen Malkowsky, Oskar Andersson
A 65-nm CMOS area optimized de-synchronization flow for sub-VT designs. VLSI-SoC 2013: 380-385 - 2012
- [c5]Pascal Andreas Meinerzhagen, Oskar Andersson
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS. ESSCIRC 2012: 321-324 - [c4]Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing. VLSI-SoC (Selected Papers) 2012: 88-106 - [c3]Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing. VLSI-SoC 2012: 159-164 - 2011
- [c2]Pascal Andreas Meinerzhagen, Oskar Andersson
Synthesis strategies for sub-VT systems. ECCTD 2011: 552-555 - [c1]Oskar Andersson
Impact of switching activity on the energy minimum voltage for 65 nm sub-VT CMOS. NORCHIP 2011: 1-4
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